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公开(公告)号：US20160380119A1
公开(公告)日：2016-12-29
申请号：US15084874
申请日：2016-03-30
Inventor： Dong Yun JUNG , Hyun Soo LEE , Sang Choon KO , Jeong-Jin KIM , Zin-Sig KIM , Jeho NA , Eun Soo NAM , Jae Kyoung MUN , Young Rak PARK , Sung-Bum BAE , Hyung Seok LEE , Woojin CHANG , Hyungyu JANG , Chi Hoon JUN
IPC: H01L29/872 , H01L29/205 , H01L29/45 , H01L21/02 , H01L23/29 , H01L29/47 , H01L29/66 , H01L21/306 , H01L29/20 , H01L23/31
CPC classification number: H01L21/0228 , H01L23/291 , H01L23/3178 , H01L29/2003 , H01L29/205 , H01L29/66212 , H01L29/872
Abstract: A first nitride semiconductor layer of a semiconductor device is provided on a substrate, a second nitride semiconductor layer is provided on the first nitride semiconductor layer, a first ohmic metal and a second ohmic metal are provided on the second nitride semiconductor layer, a recess region is provided in the second nitride semiconductor layer between the first ohmic metal and the second ohmic metal, a passivation layer covers side of the first ohmic metal and a bottom surface and sides of the recess region, and a Schottky electrode is provided on the first ohmic metal and extends into the recess region.
Abstract translation: 半导体器件的第一氮化物半导体层设置在衬底上，第二氮化物半导体层设置在第一氮化物半导体层上，第一欧姆金属和第二欧姆金属设置在第二氮化物半导体层上，凹部 在所述第一欧姆金属和所述第二欧姆金属之间的所述第二氮化物半导体层中设置钝化层，所述钝化层覆盖所述第一欧姆金属的一侧，并且所述钝化层覆盖所述凹部区域的底表面和所述侧面，并且所述第一欧姆金属的肖特基电极 金属并延伸到凹陷区域中。
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公开(公告)号：US20170213904A1
公开(公告)日：2017-07-27
申请号：US15414156
申请日：2017-01-24
Inventor： Jeho NA , Hyung Seok LEE , Chi Hoon JUN , Sang Choon KO , Myungjoon KWACK , Young Rak PARK , Woojin CHANG , Hyun-Gyu JANG , Dong Yun JUNG
IPC: H01L29/778 , H01L29/205 , H01L29/66 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/20 , H01L23/31
CPC classification number: H01L29/7787 , H01L23/315 , H01L23/3171 , H01L29/0649 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/41758 , H01L29/42364 , H01L29/42372 , H01L29/66462 , H01L29/7786
Abstract: A semiconductor device includes a semiconductor structure including a substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer, a first passivation pattern provided on the semiconductor structure, and first and second conductive patterns provided on the semiconductor structure and spaced from the first passivation pattern.
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公开(公告)号：US20170077282A1
公开(公告)日：2017-03-16
申请号：US15265647
申请日：2016-09-14
Inventor： Hyung Seok LEE , Ki Hwan KIM , Sang Choon KO , Zin-Sig KIM , Jeho NA , EUN SOO NAM , Young Rak PARK , Junbo PARK , Chi Hoon JUN , Dong Yun JUNG
IPC: H01L29/778 , H01L29/205 , H01L29/20 , H01L29/40 , H01L29/423
CPC classification number: H01L29/402 , H01L29/2003 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66462 , H01L29/7786
Abstract: Provided is an electronic device. The electronic device includes a first semiconductor layer and a second semiconductor layer sequentially stacked on a substrate and a source electrode, a gate electrode, and a drain electrode arranged on the second semiconductor layer. The electronic device further includes a field plate which is electrically connected to the source electrode and extends towards the drain electrode, wherein the field plate becomes farther away from the substrate as the field plate becomes closer to the drain electrode.
Abstract translation: 提供一种电子设备。 该电子器件包括依次堆叠在基板上的第一半导体层和第二半导体层以及设置在第二半导体层上的源电极，栅电极和漏电极。 电子装置还包括电场连接到源极并且朝向漏电极延伸的场板，其中当场板越靠近漏电极时，场板越靠近衬底。
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公开(公告)号：US20160260653A1
公开(公告)日：2016-09-08
申请号：US14872868
申请日：2015-10-01
Inventor： Chi Hoon JUN , Jeho NA , Dong Yun JUNG , Sang Choon KO , Eun Soo NAM , Hyung Seok LEE
IPC: H01L23/467
CPC classification number: H01L23/467
Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate including a cantilever configured to generate a flow of cooling media through dynamic movement, an active area on the substrate which an electronic device is provided on, an insulation layer disposed to be spaced apart from the active area on the substrate, a lower electrode on the insulation layer, a piezoelectric film on the lower electrode, and an upper electrode on the piezoelectric film.
Abstract translation: 提供一种半导体器件。 该半导体器件包括：基板，其包括悬臂，该悬臂构造成通过动态移动产生冷却介质流;基板上的有源区域，设置有电子器件;绝缘层，设置成与基板上的有源区间隔开; 绝缘层上的下电极，下电极上的压电薄膜和压电薄膜上的上电极。
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公开(公告)号：US20170062385A1
公开(公告)日：2017-03-02
申请号：US15221089
申请日：2016-07-27
Inventor： Dong Yun JUNG , Sang Choon KO , Chi Hoon JUN , Minki KIM , Jeho NA , EUN SOO NAM , Young Rak PARK , Junbo PARK , Hyun Soo LEE , Hyung Seok LEE , Hyun-Gyu JANG
IPC: H01L25/065 , H01L29/78 , H01L23/522 , H01L23/528 , H02M3/158 , H01L23/373
CPC classification number: H01L25/0652 , H01L23/367 , H01L23/3736 , H01L23/4012 , H01L23/49822 , H01L23/50 , H01L23/5226 , H01L23/528 , H01L25/072 , H01L29/78 , H02M3/156
Abstract: Disclosed is a power converting device including: a first laminate having a plurality of non-magnetic substrates which are laminated; electronic devices disposed on at least one of the non-magnetic substrates; first conductive patterns disposed on the non-magnetic substrate on which the electronic devices are disposed, the first conductive patterns being connected to the electronic devices; at least one via electrode connecting the respective first conductive patterns to each other; a second laminate disposed on one side of the first laminate and having a plurality of magnetic sheets which are laminated; second conductive patterns disposed on at least two magnetic sheets among the plurality of magnetic sheets; and at least one via electrode connecting the respective second conductive patterns to each other, wherein the first and second via electrodes are connected to each other.
Abstract translation: 公开了一种电力转换装置，包括：第一层压体，其具有层叠的多个非磁性基板; 设置在所述非磁性基板中的至少一个上的电子设备; 布置在其上设置有电子设备的非磁性基板上的第一导电图案，第一导电图案连接到电子设备; 将相应的第一导电图案彼此连接的至少一个通孔电极; 第二层压体，其设置在所述第一层叠体的一侧，并且具有层叠的多个磁性片; 设置在所述多个磁性片中的至少两个磁性片上的第二导电图案; 以及将各个第二导电图案彼此连接的至少一个通孔电极，其中所述第一和第二通孔电极彼此连接。
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Patent Agency Ranking
公开(公告)号：US20150380354A1
公开(公告)日：2015-12-31
申请号：US14845435
申请日：2015-09-04
Inventor： Byoung-Gue MIN , Sang Choon KO , Jong-Won LIM , Hokyun AHN , Hyung Sup YOON , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L23/535 , H01L23/48
CPC classification number: H01L23/535 , H01L21/02365 , H01L21/28 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
Abstract translation: 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。
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公开(公告)号：US20140363937A1
公开(公告)日：2014-12-11
申请号：US14308000
申请日：2014-06-18
Inventor： Woo Jin CHANG , Jong-Won LIM , Ho Kyun AHN , Sang Choon KO , Sung Bum BAE , Chull Won JU , Young Rak PARK , Jae Kyoung MUN , Eun Soo NAM
CPC classification number: H01L29/66901 , H01L29/2003 , H01L29/401 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
Abstract: Disclosed are a power semiconductor device and a method of fabricating the same which can increase a breakdown voltage of the device through a field plate formed between a gate electrode and a drain electrode and achieve an easier manufacturing process at the same time. The power semiconductor device according to an exemplary embodiment of the present disclosure includes a source electrode and a drain electrode formed on a substrate; a dielectric layer formed between the source electrode and the drain electrode to have a lower height than heights of the two electrodes and including an etched part exposing the substrate; a gate electrode formed on the etched part; a field plate formed on the dielectric layer between the gate electrode and the drain electrode; and a metal configured to connect the field plate and the source electrode.
Abstract translation: 公开了功率半导体器件及其制造方法，其可以通过形成在栅电极和漏电极之间的场板来增加器件的击穿电压，并且同时实现更容易的制造工艺。 根据本公开的示例性实施例的功率半导体器件包括形成在衬底上的源电极和漏电极; 形成在所述源电极和所述漏电极之间的电介质层具有比所述两个电极的高度低的高度，并且包括暴露所述衬底的蚀刻部分; 形成在蚀刻部分上的栅电极; 形成在栅电极和漏电极之间的电介质层上的场板; 以及配置成连接场板和源电极的金属。
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公开(公告)号：US20140103539A1
公开(公告)日：2014-04-17
申请号：US14021269
申请日：2013-09-09
Inventor： Byoung-Gue MIN , Sang Choon KO , Jong-Won Lim , Hokyun AHN , Hyung Sup YOON , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L21/768 , H01L23/48 , H01L21/28 , H01L21/02
CPC classification number: H01L23/535 , H01L21/02365 , H01L21/28 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/1305 , H01L2924/13091 , H01L2924/00
Abstract: A semiconductor device may include a substrate having a lower via-hole, an epitaxial layer having an opening exposing a top surface of the substrate, a semiconductor chip disposed on the top surface of the substrate and including first, second, and third electrodes, an upper metal layer connected to the first electrode, a supporting substrate disposed on the upper metal layer and having an upper via-hole, an upper pad disposed on the substrate and extending into the upper via-hole, a lower pad connected to the second electrode in the opening, and a lower metal layer covering a bottom surface of the substrate and connected to the lower pad through the lower via-hole.
Abstract translation: 半导体器件可以包括具有下通孔的衬底，具有暴露衬底的顶表面的开口的外延层，设置在衬底的顶表面上并包括第一，第二和第三电极的半导体芯片， 连接到第一电极的上金属层，设置在上金属层上并具有上通孔的支撑基板，设置在基板上并延伸到上通孔中的上焊盘，连接到第二电极的下焊盘 以及覆盖基板的底面的下金属层，并且通过下通路孔与下焊盘连接。
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公开(公告)号：US20170141704A1
公开(公告)日：2017-05-18
申请号：US15299519
申请日：2016-10-21
Inventor： Chi Hoon JUN , Sang Choon KO , Minki KIM , Jeho NA , Young Rak PARK , Junbo PARK , Hyun Soo LEE , Hyung Seok LEE , Hyun-Gyu JANG , Dong Yun JUNG
IPC: H02N2/18 , H01L41/113 , H01L29/872 , H01L29/84 , H01L29/20 , H01L29/205
CPC classification number: H02N2/186 , H01L27/20 , H01L29/2003 , H01L29/205 , H01L29/84 , H01L29/872 , H01L41/1136
Abstract: Provided is a hybrid diode device. The hybrid diode device includes a first lower nitride layer disposed on a substrate and including a first 2-dimensional electron gas (2DEG) layer, a second lower nitride layer extending from the first lower nitride layer to the outside of the substrate and including a second 2DEG layer, a first upper nitride layer disposed on the first lower nitride layer, a second upper nitride layer disposed on the second lower nitride layer, a first cap layer disposed on the first upper nitride layer, a second cap layer disposed on the second upper nitride layer, a first electrode structure connected to the first lower nitride layer and the first cap layer; and a second electrode structure connected to the second lower nitride layer and the first electrode structure. The second lower nitride layer generates electric energy through dynamic movement.
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公开(公告)号：US20160225631A1
公开(公告)日：2016-08-04
申请号：US15093814
申请日：2016-04-08
Inventor： Chi Hoon JUN , Sang Choon KO , Seok-Hwan MOON , Woojin CHANG , Sung-Bum BAE , Young Rak PARK , Je Ho NA , Jae Kyoung MUN , Eun Soo NAM
IPC: H01L21/3065 , H01L21/308 , H01L21/3205 , H01L23/367
CPC classification number: H01L21/3065 , H01L21/3081 , H01L21/32051 , H01L23/367 , H01L23/467 , H01L23/473 , H01L2924/0002 , H01L2924/00
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
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