公开(公告)号：US09245805B2

公开(公告)日：2016-01-26

申请号：US12831903

申请日：2010-07-07

Applicant: Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

Inventor： Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

IPC: H01L21/70 ,  H01L27/088 ,  H01L29/78 ,  H01L29/20 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/8256 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0847 ,  H01L29/6681 ,  H01L29/7848

Abstract: An integrated circuit structure includes an n-type fin field effect transistor (FinFET) and a p-type FinFET. The n-type FinFET includes a first germanium fin over a substrate; a first gate dielectric on a top surface and sidewalls of the first germanium fin; and a first gate electrode on the first gate dielectric. The p-type FinFET includes a second germanium fin over the substrate; a second gate dielectric on a top surface and sidewalls of the second germanium fin; and a second gate electrode on the second gate dielectric. The first gate electrode and the second gate electrode are formed of a same material having a work function close to an intrinsic energy level of germanium.

Abstract translation: 集成电路结构包括n型鳍式场效应晶体管（FinFET）和p型FinFET。 n型FinFET包括在衬底上的第一锗鳍; 顶表面上的第一栅电介质和第一锗鳍的侧壁; 以及在第一栅极电介质上的第一栅电极。 p型FinFET在衬底上包括第二个锗鳍; 在顶表面上的第二栅电介质和第二锗鳍的侧壁; 和在第二栅极电介质上的第二栅电极。 第一栅电极和第二栅极由具有接近锗的固有能级的功函数的相同材料形成。

公开(公告)号：US08941153B2

公开(公告)日：2015-01-27

申请号：US12871655

申请日：2010-08-30

Applicant: Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

Inventor： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Chang-Yun Chang ,  Feng Yuan

IPC: H01L29/76 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.

Abstract translation: 集成电路结构包括包括第一器件区域中的第一部分和第二器件区域中的第二部分的半导体衬底。 第一半导体鳍片在半导体衬底之上并且具有第一鳍片高度。 第二半导体鳍片在半导体衬底之上并且具有第二鳍片高度。 第一鳍高度大于第二翅片高度。

公开(公告)号：US08896055B2

公开(公告)日：2014-11-25

申请号：US13585436

申请日：2012-08-14

Applicant: Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

Inventor： Chih Chieh Yeh ,  Chih-Sheng Chang ,  Clement Hsingjen Wann

IPC: H01L21/336 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7857

Abstract: This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.

Abstract translation: 本说明书涉及在基板上包括基板和翅片结构的鳍状场效应晶体管（FinFET）。 鳍结构包括源极和漏极之间的沟道，其中源极，漏极和沟道具有第一类型掺杂物，并且沟道包括Ge，SiGe或III-V半导体中的至少一个。 FinFET还包括通道上的栅极介电层和栅极电介质层上的栅极。 FinFET还包括邻近栅极的衬底上的氮化物间隔物和氮化物间隔物和栅极之间以及氮化物间隔物和衬底之间的氧化物层。

公开(公告)号：US20130237026A1

公开(公告)日：2013-09-12

申请号：US13416926

申请日：2012-03-09

Applicant: Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

Inventor： Tsung-Lin Lee ,  Feng Yuan ,  Hung-Li Chiang ,  Chih Chieh Yeh

IPC: H01L29/78 ,  H01L21/30

CPC classification number: H01L21/265 ,  H01L21/26506 ,  H01L21/2654 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7847

Abstract: A method of fabricating a semiconductor device includes providing a substrate having a fin disposed thereon. A gate structure is formed on the fin. The gate structure interfaces at least two sides of the fin. A stress film is formed on the substrate including on the fin. The substrate including the stress film is annealed. The annealing provides a tensile strain in a channel region of the fin. For example, a compressive strain in the stress film may be transferred to form a tensile stress in the channel region of the fin.

公开(公告)号：US20130228830A1

公开(公告)日：2013-09-05

申请号：US13411304

申请日：2012-03-02

Applicant: Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh ,  Wei-Jen Lai

Inventor： Tsung-Lin Lee ,  Feng Yuan ,  Chih Chieh Yeh ,  Wei-Jen Lai

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L27/0886 ,  H01L21/28088 ,  H01L21/32053 ,  H01L21/32133 ,  H01L21/823431 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/785

Abstract: A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin.

公开(公告)号：US08369140B2

公开(公告)日：2013-02-05

申请号：US12018709

申请日：2008-01-23

Applicant: Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Yi-Ying Liao

Inventor： Chih-Chieh Yeh ,  Wen-Jer Tsai ,  Yi-Ying Liao

IPC: G11C11/34

CPC classification number: G11C16/0475 ,  G11C11/5671 ,  G11C16/0483 ,  G11C2211/5621

Abstract: A multi-Level Cell (MLC) can be used to store, for example, 4 bits per cell by storing two bits on each of two sides. Each side can store, e.g., four different current level states that can be determined by the number of holes injected into, e.g., nitride layer, during programming. As more holes are injected the current decreases for a given voltage. The current can be low, therefore, it can be advantageous in one embodiment to use a current amplifier. The current amplifier can be a BJT, MOS or other type of device.

Abstract translation: 多级单元（MLC）可用于通过在两侧存储两位来存储例如每单元4位。 每一侧都可以存储例如四个不同的电流状态，这些状态可以通过在编程期间注入到例如氮化物层中的空穴的数量来确定。 随着更多的孔被注入，给定电压的电流减小。 电流可能很低，因此，在一个实施例中使用电流放大器可能是有利的。 电流放大器可以是BJT，MOS或其他类型的器件。

公开(公告)号：US20120306002A1

公开(公告)日：2012-12-06

申请号：US13585436

申请日：2012-08-14

Applicant: Chih Chieh YEH ,  Chih-Sheng CHANG ,  Clement Hsingjen WANN

Inventor： Chih Chieh YEH ,  Chih-Sheng CHANG ,  Clement Hsingjen WANN

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7857

Abstract: This description relates to a fin field-effect-transistor (FinFET) including a substrate and a fin structure on the substrate. The fin structure includes a channel between a source and a drain, wherein the source, the drain, and the channel have a first type dopant, and the channel comprises at least one of a Ge, SiGe, or III-V semiconductor. The FinFET further includes a gate dielectric layer over the channel and a gate over the gate dielectric layer. The FinFET further includes a nitride spacer on the substrate adjacent the gate and an oxide layer between the nitride spacer and the gate and between the nitride spacer and the substrate.

Abstract translation: 本说明书涉及在基板上包括基板和翅片结构的鳍状场效应晶体管（FinFET）。 鳍结构包括源极和漏极之间的沟道，其中源极，漏极和沟道具有第一类型掺杂物，并且沟道包括Ge，SiGe或III-V半导体中的至少一个。 FinFET还包括通道上的栅极介电层和栅极电介质层上的栅极。 FinFET还包括邻近栅极的衬底上的氮化物间隔物和氮化物间隔物和栅极之间以及氮化物间隔物和衬底之间的氧化物层。

公开(公告)号：US20120235224A1

公开(公告)日：2012-09-20

申请号：US13428754

申请日：2012-03-23

Applicant: Chih Chieh Yeh

Inventor： Chih Chieh Yeh

IPC: H01L29/792

CPC classification number: G11C16/0466 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment cell is disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non-volatile arrays formed of the SONOS cells rely on conventional semiconductor processing. P-channel and n-channel devices may be used to form the SONOS non-volatile cells.

Abstract translation: 一种用于向SONOS单元提供非常密集，可生产，非易失性的FLASH存储器的架构，电路和方法。 使用均匀掺杂的沟道区形成SONOS存储单元。 公开了FinFET实施例单元。 由于新型SONOS细胞不依赖于扩散区域，所以可以将细胞形成三维阵列的细胞，而不会产生扩散问题。 闪存阵列通过在集成电路的局部互连层中形成NAND闪存单元的层而形成，其中金属层形成全局位线导体。 由SONOS单元形成的三维非易失性阵列依赖于常规的半导体处理。 可以使用P沟道和n沟道器件来形成SONOS非易失性单元。

公开(公告)号：US07888707B2

公开(公告)日：2011-02-15

申请号：US11923069

申请日：2007-10-24

Applicant: Yi Ying Liao ,  Wen Jer Tsai ,  Chih Chieh Yeh

Inventor： Yi Ying Liao ,  Wen Jer Tsai ,  Chih Chieh Yeh

IPC: H01L23/52

CPC classification number: G11C8/10 ,  B82Y10/00 ,  G11C11/36 ,  G11C16/02 ,  G11C2216/06 ,  H01L27/1021 ,  H01L27/115 ,  H01L29/7391 ,  H01L29/8616

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract translation: 具有电荷存储结构的门控二极管非易失性存储单元包括具有附加栅极端子的二极管结构。 示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

公开(公告)号：US07804152B2

公开(公告)日：2010-09-28

申请号：US12392454

申请日：2009-02-25

Applicant: Chih Chieh Yeh ,  Wen Jer Tsai

Inventor： Chih Chieh Yeh ,  Wen Jer Tsai

IPC: H01L21/70

CPC classification number: H01L21/76229 ,  G11C16/10 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573

Abstract: In some embodiments, a memory integrated circuit has different shallow trench isolation structures in the memory circuitry of the memory integrated circuit and the control circuitry of the memory integrated circuit. The isolation dielectric fills the trenches of the shallow trench isolation structures to different degrees.In some embodiments, a memory integrated circuit has memory circuitry with shallow trench isolation structures and intermediate regions. The memory circuitry supports a channel between neighboring nonvolatile memory devices supporting multiple current components with different orientations.In some embodiments, recessed shallow trench isolation structures are formed.

Abstract translation: 在一些实施例中，存储器集成电路在存储器集成电路的存储器电路和存储器集成电路的控制电路中具有不同的浅沟槽隔离结构。 隔离电介质以不同的程度填充浅沟槽隔离结构的沟槽。 在一些实施例中，存储器集成电路具有具有浅沟槽隔离结构和中间区域的存储器电路。 存储器电路支持在支持具有不同取向的多个电流分量的相邻非易失性存储器件之间的通道。 在一些实施例中，形成凹陷的浅沟槽隔离结构。