公开(公告)号：US12080592B2

公开(公告)日：2024-09-03

申请号：US17250835

申请日：2019-09-10

申请人： Lam Research Corporation

发明人： Hui-Jung Wu ,  Bart J. van Schravendijk ,  Mark Naoshi Kawaguchi ,  Gereng Gunawan ,  Jay E. Uglow ,  Nagraj Shankar ,  Gowri Channa Kamarthy ,  Kevin M. McLaughlin ,  Ananda K. Banerji ,  Jialing Yang ,  John Hoang ,  Aaron Lynn Routzahn ,  Nathan Musselwhite ,  Meihua Shen ,  Thorsten Bernd Lill ,  Hao Chi ,  Nicholas Dominic Altieri

IPC分类号： H01L21/336 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L29/788 ,  H10B41/20 ,  H10B41/35

CPC分类号： H01L21/76846 ,  H01L21/0217 ,  H01L21/02263 ,  H01L21/31105 ,  H01L21/76816 ,  H01L29/7889 ,  H10B41/20 ,  H10B41/35

摘要： Methods for forming patterned multi-layer stacks including a metal-containing layer are provided herein. Methods involve using silicon-containing non-metal materials in a multi-layer stack including one sacrificial layer to be later removed and replaced with metal while maintaining etch contrast to pattern the multi-layer stack and selectively remove the sacrificial layer prior to depositing metal. Methods involve using silicon oxycarbide in lieu of silicon nitride, and a sacrificial non-metal material in lieu of a metal-containing layer, to fabricate the multi-layer stack, pattern the multi-layer stack, selectively remove the sacrificial non-metal material to leave spaces in the stack, and deposit metal-containing material into the spaces. Sacrificial non-metal materials include silicon nitride and doped polysilicon, such as boron-doped silicon.

公开(公告)号：US11980031B2

公开(公告)日：2024-05-07

申请号：US17128915

申请日：2020-12-21

申请人： Kioxia Corporation

发明人： Takashi Ishida ,  Yoshiaki Fukuzumi ,  Takayuki Okada ,  Masaki Tsuji

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L27/115 ,  H01L29/10 ,  H01L29/423 ,  H01L29/788 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC分类号： H10B43/27 ,  H01L29/1037 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/35

摘要： According to an embodiment, a non-volatile memory device includes first electrodes stacked on an underlying layer, a second electrode provided on the first electrodes, a semiconductor layer extending in a first direction from the underlying layer to the second electrode, and a memory film provided between each of the first electrodes and the semiconductor layer. The semiconductor layer includes a first portion adjacent to the first electrodes and a second portion adjacent to the second electrode. The second portion has a thickness thinner than a thickness of the first portion in a second direction perpendicular to the first direction.

公开(公告)号：US11848239B2

公开(公告)日：2023-12-19

申请号：US16925918

申请日：2020-07-10

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chieh-Wei Chen ,  Jian-Jou Lian ,  Tzu-Ang Chiang ,  Chun-Neng Lin ,  Ming-Hsi Yeh

IPC分类号： H01L21/8234 ,  H01L21/027 ,  H01L21/336 ,  G03F1/46 ,  G03F7/09 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823431 ,  G03F1/46 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/82345 ,  H01L29/66795

摘要： A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.

公开(公告)号：US11757020B2

公开(公告)日：2023-09-12

申请号：US16941445

申请日：2020-07-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wan-Yi Kao ,  Che-Hao Chang ,  Yung-Cheng Lu ,  Chi On Chui

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/417 ,  H01L21/385 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC分类号： H01L29/66795 ,  H01L21/0228 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7851 ,  H01L21/385 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/785

摘要： A method includes forming a fin extending from a substrate; forming an first isolation region along opposing sidewalls of the fin; forming a gate structure over the fin; forming an epitaxial source/drain region in the fin adjacent the gate structure; forming an etch stop layer over the epitaxial source/drain region and over the gate structure; forming a protection layer over the etch stop layer, the protection layer including silicon oxynitride; and forming a second isolation material over the protection layer, wherein forming the second isolation material reduces a nitrogen concentration of the protection layer.

公开(公告)号：US11742307B2

公开(公告)日：2023-08-29

申请号：US17590592

申请日：2022-02-01

申请人： Ovonyx Memory Technology, LLC

发明人： John Moore ,  Joseph F. Brooks

IPC分类号： H01L23/00 ,  H01L45/00 ,  H01L27/24 ,  H01L21/768 ,  H01L21/336 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L24/06 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53257 ,  H01L24/03 ,  H01L24/05 ,  H10B63/00 ,  H10B63/30 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/231 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8825 ,  H01L2224/0311 ,  H01L2224/05014 ,  H01L2224/0555 ,  H01L2224/05147 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/06179 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01016 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/1443 ,  H01L2924/19041 ,  H01L2924/2064 ,  H01L2224/05647 ,  H01L2924/00014

摘要： A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

公开(公告)号：US11502194B2

公开(公告)日：2022-11-15

申请号：US17263207

申请日：2019-07-25

申请人： CSMC TECHNOLOGIES FAB2 CO., LTD.

发明人： Tse-huang Lo

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

摘要： An MOSFET manufacturing method, comprising: etching an oxide layer and a silicon nitride layer on a first conductivity type well region, and forming an opening exposing the first conductivity type well region; etching the first conductivity type well region to form a first trench; depositing a medium oxide layer and performing back etching; etching the first conductivity type well region to form a second trench that is connected to the first trench, and forming a grid on an inner wall of the second trench, forming a second conductivity type well region in the first conductivity type well region at the bottom of the second trench, and forming a source in the second conductivity type well region; and removing the oxide layer and the silicon nitride layer, and forming a drain at the first conductivity type well region outside of the trench.

公开(公告)号：US11462540B2

公开(公告)日：2022-10-04

申请号：US17142176

申请日：2021-01-05

申请人： Intel Corporation

发明人： Peter L. D. Chang ,  Uygar E. Avci ,  David Kencke ,  Ibrahim Ban

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/16

摘要： A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is described. In one embodiment, a p type back gate with a thicker insulation is used with a thinner insulated n type front gate. Processing, which compensates for misalignment, which allows the different oxide and gate materials to be fabricated is described.

公开(公告)号：US11444118B2

公开(公告)日：2022-09-13

申请号：US16568392

申请日：2019-09-12

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： Hubert Bono ,  Julia Simon

IPC分类号： H01L21/26 ,  H01L21/336 ,  H01L27/15 ,  H01L25/16 ,  H01L27/144 ,  H01L31/0224 ,  H01L31/18 ,  H01L33/38 ,  H01L33/58 ,  H01L33/00

摘要： A method of manufacturing an optoelectronic device, including: a) transferring, onto a connection surface of a control circuit, an active diode stack including at least first and second semiconductor layers of opposite conductivity types, so that the second semiconductor layer in the stack faces the connection surface of the control circuit and is separated from the connection surface of the control circuit by at least one insulating layer; b) forming in the active stack trenches delimiting a plurality of diodes, the trenches extending through the insulating layer and emerging onto the connection surface of the control circuit; and c) forming in the trenches metallizations connecting the second semiconductor layer to the connection surface of the control circuit.

公开(公告)号：US11437485B2

公开(公告)日：2022-09-06

申请号：US17131518

申请日：2020-12-22

申请人： HRL Laboratories, LLC

发明人： Yu Cao ,  Rongming Chu ,  Zijian Ray Li

IPC分类号： H01L21/336 ,  H01L29/51 ,  H01L29/20 ,  H01L29/778 ,  H01L29/78 ,  H01L29/417 ,  H01L29/43 ,  H01L29/06 ,  H01L21/28 ,  H01L29/423

摘要： A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.

公开(公告)号：US11296289B2

公开(公告)日：2022-04-05

申请号：US16203831

申请日：2018-11-29

申请人： Samsung Electronics Co., Ltd.

发明人： Joo Young Kim ,  Byong Gwon Song ,  Jeong Il Park ,  Jiyoung Jung

IPC分类号： H01L51/10 ,  H01L27/28 ,  H01L21/84 ,  H01L51/05 ,  H01L51/00 ,  H01L29/423 ,  H01L51/40 ,  H01L21/336

摘要： A thin film transistor includes a gate electrode, a semiconductor layer overlapped with the gate electrode, a gate insulating layer between the gate electrode and the semiconductor layer, and a source electrode and a drain electrode electrically connected to the semiconductor layer. The semiconductor layer includes a plurality of holes. The gate insulating layer may include a plurality of recess portions at a surface of the gate insulating layer facing the semiconductor layer. A method of manufacturing the thin film transistor is provided. A thin film transistor array panel and an electronic device may include the thin film transistor.