公开(公告)号：US11361965B1

公开(公告)日：2022-06-14

申请号：US17074486

申请日：2020-10-19

Applicant: HRL Laboratories, LLC

Inventor： Danny M. Kim ,  Rongming Chu ,  Yu Cao ,  Thaddeus D. Ladd

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/06

Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.

公开(公告)号：US10937650B1

公开(公告)日：2021-03-02

申请号：US16676341

申请日：2019-11-06

Applicant: HRL Laboratories, LLC

Inventor： Danny M. Kim ,  Rongming Chu ,  Yu Cao ,  Thaddeus D. Ladd

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/06

Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.

公开(公告)号：US10659032B2

公开(公告)日：2020-05-19

申请号：US16180434

申请日：2018-11-05

Applicant: HRL Laboratories, LLC

Inventor： Brian Hughes ,  Rongming Chu

IPC: H01L21/66 ,  H03K17/041 ,  H01L27/06 ,  H01L27/085 ,  H01L23/64 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H02M1/08 ,  H02M7/00 ,  H01L21/8252

Abstract: A half bridge circuit includes a sapphire substrate, a GaN upper switch on the sapphire substrate, a GaN lower switch on the sapphire substrate and coupled to the GaN upper switch, a first conductor coupled to the upper switch, a second conductor coupled to the lower switch, and a capacitor. A portion of the first conductor and a portion of the second conductor are on a plane vertically separated from the upper switch and the lower switch by a height, and the capacitor is coupled between the portion of the first conductor and the portion of the second conductor.

公开(公告)号：US10276712B2

公开(公告)日：2019-04-30

申请号：US15345406

申请日：2016-11-07

Applicant: HRL Laboratories, LLC

Inventor： Rongming Chu

IPC: H01L31/0256 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/40 ,  H01L29/778 ,  H01L29/51

Abstract: A field effect transistor (FET) includes a III-nitride channel layer, a III-nitride barrier layer on the channel layer, a first dielectric on the barrier layer, a first gate trench extending through the first dielectric, and partially or entirely through the barrier layer, a second dielectric on a bottom and walls of the first gate trench, a source electrode on a first side of the first gate trench, a drain electrode on a second side of the first gate trench opposite the first side, a first gate electrode on the second dielectric and filling the first gate trench, a third dielectric between the first gate trench and the drain electrode, a second gate trench extending through the third dielectric and laterally located between the first gate trench and the drain electrode, and a second gate electrode filling the second gate trench.

公开(公告)号：US20160276161A1

公开(公告)日：2016-09-22

申请号：US14762097

申请日：2014-06-11

Applicant: HRL LABORATORIES, LLC

Inventor： Mary Y. CHEN ,  Rongming Chu

IPC: H01L21/285 ,  H01L21/02 ,  H01L29/20 ,  H01L29/45 ,  H01L29/778

CPC classification number: H01L21/28575 ,  H01L21/0217 ,  H01L21/02274 ,  H01L29/2003 ,  H01L29/452 ,  H01L29/7786

Abstract: A method of forming an Ohmic contact including forming a Ta layer in a contact area of a barrier, forming a Ti layer on the first Ta layer, and forming an Al layer on the Ti layer, wherein the barrier layer comprises AlGaN having a 10% to 40% Al composition and a thickness in a range between 30 Å to 100 Å, and wherein the barrier layer is on a channel layer comprising GaN.

Abstract translation: 一种形成欧姆接触的方法，包括在阻挡层的接触区域中形成Ta层，在第一Ta层上形成Ti层，并在Ti层上形成Al层，其中阻挡层包括具有10％ 至40％的Al组成，并且在30埃至100埃的范围内的厚度，并且其中该阻挡层位于包含GaN的沟道层上。

公开(公告)号：US10651306B2

公开(公告)日：2020-05-12

申请号：US15687369

申请日：2017-08-25

Applicant: HRL Laboratories, LLC

Inventor： Rongming Chu ,  Yu Cao

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20 ,  H01L29/207 ,  H01L29/423

Abstract: A III-nitride power handling device and the process of making the III-nitride power handling device are disclosed that use digital alloys as back barrier layer to mitigate the strain due to lattice mismatch between the channel layer and the back barrier layer and to provide increased channel conductivity. An embodiment discloses a GaN transistor using a superlattice binary digital alloy as back barrier comprising alternative layers of AlN and GaN. Other embodiments include using superlattice structures with layers of GaN and AlGaN as well as structures using AlGaN/AlGaN stackups that have different Aluminum concentrations. The disclosed device has substantially increased channel conductivity compared to traditional analog alloy back barrier devices.

公开(公告)号：US10283358B2

公开(公告)日：2019-05-07

申请号：US15980554

申请日：2018-05-15

Applicant: HRL Laboratories, LLC

Inventor： Rongming Chu ,  Yu Cao

IPC: H01L29/12 ,  H01L21/02 ,  H01L29/20 ,  H01L29/861 ,  H01L29/66 ,  H01L29/06

Abstract: Lateral PN junctions and diodes and transistors comprising lateral PN junctions and methods used in making such devices are disclosed. A method of fabricating a lateral PN junction, can comprise: conformally growing p−GaN material on a n−GaN vertical surface extending vertically from an n−GaN horizontal surface on an n−GaN drift layer to form a first PN junction, wherein the n−GaN horizontal surface extends horizontally from the n−GaN vertical surface and the n−GaN horizontal surface has a layer of dielectric material formed on the n−GaN horizontal surface that extends from the p−GaN surface.

公开(公告)号：US09929243B1

公开(公告)日：2018-03-27

申请号：US14816850

申请日：2015-08-03

Applicant: HRL LABORATORIES, LLC.

Inventor： Andrea Corrion ,  Keisuke Shinohara ,  Miroslav Micovic ,  Rongming Chu ,  David F. Brown ,  Alexandros D. Margomenos ,  Shawn D. Burnham

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/78 ,  H01L29/49 ,  H01L29/205

CPC classification number: H01L29/42376 ,  H01L21/28587 ,  H01L21/765 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/407 ,  H01L29/495 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7784 ,  H01L29/7786 ,  H01L29/78

Abstract: A method of making a stepped field gate for an FET including forming a first passivation layer on a barrier layer, defining a first field plate by using electron beam (EB) lithography and by depositing a first negative EB resist, forming a second passivation layer over first negative EB resist and the first passivation layer, planarizing the first negative EB resist and the second passivation layer, defining a second field plate by using EB lithography and by depositing a second negative EB resist connected to the first negative EB resist, forming a third passivation layer over second negative EB resist and the second passivation layer, planarizing the second negative EB resist and the third passivation layer, removing the first and second negative EB resist, and forming a stepped field gate by using lithography and plating in a void left by the removed first and second negative EB resist.

公开(公告)号：US09899482B2

公开(公告)日：2018-02-20

申请号：US15093710

申请日：2016-04-07

Applicant: HRL Laboratories, LLC

Inventor： Rongming Chu ,  Yu Cao ,  Zijian Li ,  Adam J. Williams

IPC: H01L29/15 ,  H01L29/205 ,  H01L29/872 ,  H01L29/66 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/205 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/66212 ,  H01L29/872

Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.

公开(公告)号：US09761438B1

公开(公告)日：2017-09-12

申请号：US14272993

申请日：2014-05-08

Applicant: HRL Laboratories, LLC

Inventor： Rongming Chu ,  Xu Chen

IPC: H01L21/336 ,  H01L21/318 ,  H01L29/778 ,  H01L29/20 ,  H01L21/02 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/201 ,  H01L29/205

CPC classification number: H01L21/0217 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L23/291 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure comprising a layer of a III-N material and at least a portion of said layer being covered by a passivation layer, wherein the passivation layer comprises a first layer of SiN formed on said at least a portion of said III-N material layer and a second layer of SiN formed on said first layer of SiN; the first SiN layer having a first thickness and generating tensile stress in the structure and the second SiN layer having a second thickness and generating compressive stress in the structure.