公开(公告)号：US20240363613A1

公开(公告)日：2024-10-31

申请号：US18770392

申请日：2024-07-11

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Kuo-Ming WU ,  Ming-Che LEE ,  Hau-Yi HSIAO ,  Cheng-Hsien CHOU ,  Sheng-Chau CHEN ,  Cheng-Yuan TSAI

IPC分类号： H01L25/00 ,  H01L21/268 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532

CPC分类号： H01L25/50 ,  H01L21/268 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/5329 ,  H01L24/94 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3083 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0557 ,  H01L2224/08145 ,  H01L2224/94

摘要： A bonded assembly of a first wafer including a first semiconductor substrate and a second wafer including a second semiconductor substrate may be formed. The second semiconductor substrate may be thinned to a first thickness, and an inter-wafer moat trench may be formed at a periphery of the bonded assembly. A protective material layer may be formed in the inter-wafer moat trench and over the backside surface of the second semiconductor substrate. A peripheral portion of the second semiconductor substrate located outside the inter-wafer moat trench may be removed, and a cylindrical portion of the protective material layer laterally surrounds a remaining portion of the bonded assembly. The second semiconductor substrate may be thinned to a second thickness by performing at least one thinning process while the cylindrical portion of the protective material layer protects the remaining portion of the bonded assembly.

公开(公告)号：US20240363435A1

公开(公告)日：2024-10-31

申请号：US18766003

申请日：2024-07-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ta-Chun Lin ,  Kuo-Hua Pan ,  Jhon Jhy Liaw

IPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure provides a method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area, forming a first active region in the first circuit area and a second active region on the second circuit area, forming first gate stacks on the first active region and second gate stacks on the second active region, performing a plurality of implantation processes to introduce a doping species to the first active region with a first dosage and to the second active region with a second dosage different from the first dosage, and forming first source/drain features within first source/drain regions of the first active region and second source/drain features within second source/drain regions of the second active region.

公开(公告)号：US20240363355A1

公开(公告)日：2024-10-31

申请号：US18771442

申请日：2024-07-12

申请人： LAM RESEARCH CORPORATION

发明人： Ji ZHU ,  Mark KAWAGUCHI ,  Nathan MUSSELWHITE

IPC分类号： H01L21/306 ,  H01L21/02

CPC分类号： H01L21/30604 ,  H01L21/02057

摘要： A method for treating a substrate in a processing chamber includes forming a conformal liquid layer on the substrate by concurrently supplying a vaporized solvent and a reactive gas including a halogen species to the processing chamber. The method includes forming a reactive liquid layer on the substrate due to the conformal liquid layer adsorbing the reactive gas and etching at least a portion of the substrate by the reactive liquid layer. The etching forms a gaseous byproduct without forming residue.

公开(公告)号：US20240363345A1

公开(公告)日：2024-10-31

申请号：US18441352

申请日：2024-02-14

申请人： Applied Materials, Inc.

发明人： Chang Seok KANG ,  Raman GAIRE ,  Hsueh Chung CHEN ,  In Soo JUNG ,  Houssam LAZKANI ,  Balasubramanian PRANATHARTHIHARAN

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/306

CPC分类号： H01L21/02645 ,  H01L21/02532 ,  H01L21/2003 ,  H01L21/306

摘要： A method for manufacturing a memory device includes depositing a seed layer in a memory hole extending through a memory stack. The seed layer includes particles, such as silicon particles. The seed layer is etched to produce etched particles. The etched particles act as nuclei for the growth of a crystalline channel material in the memory hole.

公开(公告)号：US20240355633A1

公开(公告)日：2024-10-24

申请号：US18762702

申请日：2024-07-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wen-Yen Chen

IPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC分类号： H01L21/3086 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3088 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

摘要： A method includes forming an etching mask to cover a mandrel, a first spacer, and a second spacer, and the first spacer and the second spacer are in contact with opposing sidewalls of the mandrel. The etching mask is then patterned, and includes a first portion covering the first spacer, a second portion covering the second spacer, and a bridge portion connecting the first portion to the second portion. The bridge portion has first sidewalls. A first etching process is performed on the mandrel using the etching mask to define pattern, and after the first etching process, the mandrel includes a second bridge portion having second sidewalls vertically aligned to corresponding ones of the first sidewalls. After the mandrel is etched-through, a second etching process is performed to laterally recess the second bridge portion of the mandrel.

公开(公告)号：US20240355617A1

公开(公告)日：2024-10-24

申请号：US18757803

申请日：2024-06-28

申请人： Tokyo Electron Limited

发明人： Hiroshi Nakamura ,  Masahide Tadokoro ,  Masashi Enomoto

IPC分类号： H01L21/02 ,  B05C5/02 ,  B05C11/00 ,  G03F7/16 ,  G03F7/20 ,  H01L21/302 ,  H01L21/306 ,  H01L21/66 ,  H01L21/67

CPC分类号： H01L21/02343 ,  B05C5/022 ,  B05C11/00 ,  G03F7/162 ,  G03F7/2028 ,  H01L21/302 ,  H01L21/306 ,  H01L21/6708 ,  H01L21/6715 ,  H01L21/67253 ,  H01L21/67259 ,  H01L21/67276 ,  H01L21/67288 ,  H01L22/12 ,  H01L22/20 ,  G03F7/168

摘要： A substrate processing apparatus includes a periphery removal unit configured to remove a peripheral portion of a film formed on a surface of a substrate; a profile acquisition unit configured to acquire a removal width profile indicating a relationship between a position in a circumferential direction of the substrate and a width of a portion of the substrate from which the film is removed; and a factor estimation unit configured to output factor information indicating a factor of an error in the width based on the removal width profile.

公开(公告)号：US12125852B2

公开(公告)日：2024-10-22

申请号：US18360895

申请日：2023-07-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Huan-Chieh Su ,  Li-Zhen Yu ,  Chun-Yuan Chen ,  Shih-Chuan Chiu ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC分类号： H01L27/088 ,  H01L21/027 ,  H01L21/306 ,  H01L21/308

CPC分类号： H01L27/0886 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/3086

摘要： A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

公开(公告)号：US20240342858A1

公开(公告)日：2024-10-17

申请号：US18753038

申请日：2024-06-25

申请人： KURARAY CO., LTD.

发明人： Azusa OSHITA ,  Mitsuru KATO ,  Minori TAKEGOSHI ,  Chihiro OKAMOTO ,  Shinya KATO

IPC分类号： B24B37/24 ,  C08G18/69 ,  C08G18/83 ,  H01L21/306

CPC分类号： B24B37/24 ,  C08G18/692 ,  C08G18/83 ,  H01L21/30625

摘要： A modification method of a polyurethane, including the steps of: preparing a polyurethane having an ethylenically unsaturated bond; and treating the polyurethane with a liquid containing a compound having a conjugated double bond, or a modification method of a polyurethane, including the steps of: preparing a polyurethane having a conjugated double bond; and treating the polyurethane with a liquid containing a compound having an ethylenically unsaturated bond is used.

公开(公告)号：US12119403B2

公开(公告)日：2024-10-15

申请号：US18355997

申请日：2023-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Max Liu ,  Yen-Ming Peng ,  Wei-Shuo Ho

IPC分类号： H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/66 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/7848 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02667 ,  H01L21/30625 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.

公开(公告)号：US12119232B2

公开(公告)日：2024-10-15

申请号：US17847971

申请日：2022-06-23

申请人： Lam Research Corporation

发明人： Juline Shoeb ,  Alexander Miller Paterson ,  Ying Wu

IPC分类号： H01L21/306 ,  H01J37/305 ,  H01J37/32 ,  H01L21/3065

CPC分类号： H01L21/3065 ,  H01J37/3053 ,  H01J37/321

摘要： Systems and methods for etching different features in a substantially equal manner are described. One of the methods includes applying a low frequency bias signal during a low TCP state and applying a high frequency bias signal during a high TCP state. The application of the low frequency bias signal during the low TCP state facilitates generation of hot neutrals, which are used to increase an etch rate of etching dense features compared to an etch rate for etching isolation features. The application of the high frequency bias signal during the high TCP state facilitates generation of ions to increase an etch rate of etching the isolation features compared to an etch rate of etching the dense features. After applying the low frequency bias signal during the low TCP state and the high frequency bias signal during the high TCP state, the isolation and dense features are etched similarly.