公开(公告)号：US3752715A

公开(公告)日：1973-08-14

申请号：US3752715D

申请日：1971-11-15

Applicant: IBM

Inventor： ANTIPOV I ,  OBERAI A

IPC: H01L21/331 ,  H01L21/8228 ,  H01L27/082 ,  H01L29/417 ,  H01L29/73 ,  H01L7/44 ,  H01L7/64

CPC classification number: H01L21/82285 ,  H01L27/0826 ,  Y10S148/037 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/151

Abstract: COMPLEMENTARY NPN AND PNP TRANSISTORS ARE PREPARED SIMULTANEOUSLY WHICH HAVE PROPERTIES OF A HIGH FREQUENCY RESPONSE. SELECTED IMPURITY CONCENTRATIONS ARE EMPLOYED WHEREBY THE SECOND EMITTER DIFFUSION IS PERFORMED WITH THE FIRST EMITTER AREA UNMASKET. THIS ELIMINATES AND EMITTER CONTACT OPENING STEP SUCH THAT EACH CONTACT AREA AND EMITTER ARE CO-EXTENSIVE. OTHER CIRCUIT COMPONENTS SUCH AS RESISTORS AND DIODES ARE ALSO FORMED DURING THE FORMATION OF THE NPN AND PNP TRANSISTORS.

公开(公告)号：US3423822A

公开(公告)日：1969-01-28

申请号：US3423822D

申请日：1967-02-27

Applicant: NORTHERN ELECTRIC CO

Inventor： DAVIDSON IAN A ,  HANTUSCH GERALD H ,  MAY GEORGE A

IPC: H01L21/82 ,  H01L27/02 ,  H01L7/64 ,  H01L19/00

CPC classification number: H01L27/0207 ,  H01L21/82 ,  H01L22/22

公开(公告)号：US3884732A

公开(公告)日：1975-05-20

申请号：US39804073

申请日：1973-09-17

Applicant: IBM

Inventor： BAITINGER UTZ G ,  NAJMANN KNUT K

IPC: G11C11/411 ,  H01L27/102 ,  H01L29/10 ,  H01L7/44 ,  H01L7/64 ,  H01L29/72

CPC classification number: H01L29/1004 ,  G11C11/4116 ,  H01L27/1025 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/085 ,  Y10S148/145 ,  Y10S148/151

Abstract: A monolithic storage matrix having cells formed of multi-emitter transistors in which one emitter of each transistor forms part of the storage circuit and the other emitter of each transistor is coupled to the accessing and retrieval circuits. The transistors portions for storage are formed with bases of a given width and the transistors portions coupled to the accessing and retrieving circuits have a lesser width so that short access times are obtained while the stability of the storage circuit is maintained.

公开(公告)号：US3738877A

公开(公告)日：1973-06-12

申请号：US3738877D

申请日：1970-08-24

Applicant: MOTOROLA INC

Inventor： DAVIDSOHN U

IPC: H01L21/00 ,  H01L21/762 ,  H01L21/82 ,  H01L21/8222 ,  H01L27/00 ,  H01L27/06 ,  H01L29/00 ,  H01L7/00 ,  H01L7/64 ,  H01L19/00

CPC classification number: H01L27/00 ,  H01L21/00 ,  H01L21/76297 ,  H01L21/82 ,  H01L21/8222 ,  H01L27/0664 ,  H01L29/00 ,  Y10S148/036 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/139

Abstract: VARIOUS DEVICES ARE DESCRIBED HEREIN UTILIZING ANISOTROPIC ETCHING AND DIELECTRIC ISOLATIONS AS MEANS FOR LIMITING AREAS OF EITHER CONDUCTIVITY TYPE SEMICONDUCTOR MATERIAL. SURFACE JUNCTIONS NORMALLY FOUND IN THE DIFFUSED SEMICONDUCTOR DEVICES OF THE PRIOR ART ARE ALSO ELIMINATED BY THE USE OF OVERLAP DIFFUSION TECHNIQUES. ANISOTROPIC ETCHING IS EMPLOYED IN CERTAIN OF THE DEVICES FOR ATTAINING BURIED PN JUNCTIONS.

公开(公告)号：US3716425A

公开(公告)日：1973-02-13

申请号：US3716425D

申请日：1970-08-24

Applicant: MOTOROLA INC

Inventor： DAVIDSOHN U

IPC: H01L21/762 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L7/00 ,  H01L7/64 ,  H01L11/00

CPC classification number: H01L27/0664 ,  H01L21/76297 ,  H01L21/8222 ,  H01L29/0821 ,  Y10S148/031 ,  Y10S148/036 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/122 ,  Y10S148/151

Abstract: An integrated device and/or circuit and the method for making such is disclosed employing a plurality of fully insulated islands having plane walls. Selected diffusion steps are made overlapping certain of the islands and certain of the other diffusion steps.

Abstract translation: 公开了一种使用多个具有平面壁的完全绝缘的岛的集成装置和/或电路及其制造方法。 使选定的扩散步骤与某些岛屿和某些其他扩散步骤重叠。

公开(公告)号：US3562032A

公开(公告)日：1971-02-09

申请号：US3562032D

申请日：1968-02-05

Applicant: PHILIPS CORP

Inventor： FROUIN JEAN-CLAUDE ,  BREBISSON MICHEL DE

IPC: H01L21/761 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/082 ,  H01L7/44 ,  H01L7/64

CPC classification number: H01L27/0826 ,  H01L21/761 ,  H01L21/8224 ,  H01L21/82285 ,  H01L27/0821 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/096 ,  Y10S148/151

Abstract: A METHOD FOR MAKING A MONOLITHIC INTEGRATED CIRCUIT IS DESCRIBED. THE CIRCUIT INCLUDES VERTICAL COMPLEMENTARY TRANSISTORS IN ISOLATED ISLANDS. THE EMITTER OF THE PNP TRANSISTOR IS DIFFUSED SIMULTANEOUSLY IWTH THE ISOLATION WALLS DEFINING THE ISLANDS. THE BASE OF THE PNP TRANSISTOR IS FORMED BY THE ISLAND REGION ADJACENT THE SUBSTRATE, WHICH ACTS AS A COLLECTOR. THE NPN TRANSISTOR IS THE USUAL DOUBLE-DIFFUSED TRANSISTOR.

公开(公告)号：US3843425A

公开(公告)日：1974-10-22

申请号：US29521272

申请日：1972-10-05

Applicant: RCA CORP

Inventor： KATNACK F

IPC: H01L21/00 ,  H01L23/482 ,  H01L29/00 ,  H01L7/64

CPC classification number: H01L21/00 ,  H01L23/4824 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/085 ,  Y10S148/122 ,  H01L2924/00

Abstract: 1. A METHOD FOR MAKING A SEMICONDUCTOR DEVICE, COMPRISING THE STEPS OF: PROVIDING A SEMICONDUCTOR BODY HAVING A REGION OF A FIRST CONDUCTIVITY-TYPE THEREIN ADJACENT ONE SURFACE OF THE BODY, WITH AN INSULATING COATING ON SAID SURFACE; FORMING A COMMUNICATING SLOT IN SAID COATING WHICH EXTENDS TO SAID SURFACE; FORMING A SEMICONDUCTOR LAYER OF SAID FIRST CONDUCTIVITY TYPE IN SAID SLOT WHICH CONTACTS SAID REGION; DIFFUSING IMPURITIES OF SAID ONE CONDUCTIVITY-TYPE INTO SAID SEMICONDUCTOR LAYER SO THAT SAID LAYER IS HIGHLY CONDUCTIVE WITH RESPECT TO SAID REGION; AND DIFFUSING A PLURALITY OF SEGMENTS OF A SECOND CONDUCTIVITY-TYPE INTO SAID REGION FROM SAID SURFACE IS SPACED RELATION TO SAID SEMICONDUCTOR LAYER.

公开(公告)号：US3734787A

公开(公告)日：1973-05-22

申请号：US3734787D

申请日：1970-01-09

Applicant: IBM

Inventor： DHAKA V ,  KROLIKOWSKI W

IPC: H01L27/04 ,  H01L21/82 ,  H01L21/822 ,  H01L29/93 ,  H01L7/64 ,  H01L5/00 ,  H01L19/00

CPC classification number: H01L21/82 ,  H01L29/93 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/151 ,  Y10S438/901

Abstract: A diffused junction capacitor having two P N junctions, one in the semiconductor substrate and one in an epitaxial layer thereon and exhibiting high capacitance per unit area. A method for forming such a capacitor makes use of the fact that the outdiffusion rate for boron is much faster than the outdiffusion rate for arsenic, whereby, for instance, boron and arsenic diffused into the surface of a semiconductor wafer can, after the growth of an N epitaxial layer, be diffused into the N epitaxial layer. Since the boron outdiffuses much faster, it will cover a larger area than the arsenic outdiffusion. This will, in turn, result in two P -N junctions, one in the substrate and one in the N epitaxial layer.

Abstract translation: 具有两个P + N +结的扩散结电容器，一个在半导体衬底中，一个在外延层中，并且每单位面积具有高电容。

公开(公告)号：US3723199A

公开(公告)日：1973-03-27

申请号：US3723199D

申请日：1969-11-10

Applicant: IBM

Inventor： VORA M

IPC: H01L21/00 ,  H01L21/74 ,  H01L27/00 ,  H01L29/08 ,  H01L7/00 ,  H01L7/64 ,  H01L19/00

CPC classification number: H01L29/0826 ,  H01L21/00 ,  H01L21/74 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/098 ,  Y10S148/145 ,  Y10S148/151 ,  Y10S257/919

Abstract: A SUBCOLLECTOR WINDOW IS OPENED IN AN OXIDE COVERED P- SIALICON SUBSTRATE. TWO N DOPANTS OF DIFFERENT DIFFUSION RATES (ARSENIC AND PHOSPHOROUS) ARE DIFFUSED THROUGH THE WINDOW INTO THE SUBSTRATE. THE OXIDE COVERING IS REMOVED AND A P- SILICON EPITAXIAL LAYER IS DEPOSITED ON THE SUBSTRATE AND REOXIDIZED. DURING THE REOXIDATION CYCLE, THE PHSOPHOROUS AND ARSENIC ARE OUT-DIFFUSED, THE PHOSPHORUS REACHING THE TOP SURFACE OF THE EPITAXIAL LAYER TO PRODUCE AN N POCKET IN THE P- EPITAXIAL LAYER AND SUBSTRATE, THE POCKET HAVING A HEAVILY DOPED N+ REGION ADJACENT THE

EPITAXIAL LAYER-SUBSTRATE INTERFACE. BASE AND EMITTER DIFFUSIONS ARE MADE WITHIN THE N POCKET TO FORM A TRANSISTOR.

公开(公告)号：US3484341A

公开(公告)日：1969-12-16

申请号：US3484341D

申请日：1966-09-07

Applicant: ITT

Inventor： DEVITT DOUGLAS J

IPC: H01L21/288 ,  H01L23/485 ,  H01L7/64 ,  C23B5/48

CPC classification number: H01L21/2885 ,  H01L23/485 ,  H01L2224/13 ,  Y10S148/02 ,  Y10S148/055