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    Method of making semiconductor devices through overlapping diffusions
    2.
    发明授权
    Method of making semiconductor devices through overlapping diffusions 失效
    通过重叠扩散制造半导体器件的方法

    公开(公告)号：US3800195A

    公开(公告)日：1974-03-26

    申请号：US27920772

    申请日：1972-08-09

    Applicant: MOTOROLA INC

    Inventor： DAVIDSOHN U

    IPC: H01L21/762 ,  H01L21/8222 ,  H01L27/102 ,  H01L19/00

    CPC classification number: H01L27/1022 ,  H01L21/76297 ,  H01L21/8222

    Abstract: An integrated device and/or circuit and the method for making such is disclosed employing a plurality of fully insulated islands having plane walls. Selected diffusion steps are made overlapping certain of the islands and certain of the other diffusion steps.

    Abstract translation: 公开了一种使用多个具有平面壁的完全绝缘的岛的集成装置和/或电路及其制造方法。 使选定的扩散步骤与某些岛屿和某些其他扩散步骤重叠。

    Methods of forming self aligned transistor structure having polycrystalline contacts
    3.
    发明授权
    Methods of forming self aligned transistor structure having polycrystalline contacts 失效
    形成具有多晶体接触的自对准晶体管结构的方法

    公开(公告)号：US3847687A

    公开(公告)日：1974-11-12

    申请号：US30676272

    申请日：1972-11-15

    Applicant: MOTOROLA INC

    Inventor： DAVIDSOHN U ,  AJAMIE A

    IPC: H01L21/00 ,  H01L21/8222 ,  H01L23/485 ,  H01L27/00 ,  H01L29/00 ,  H01L7/44

    CPC classification number: H01L27/00 ,  H01L21/00 ,  H01L21/8222 ,  H01L23/485 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/106 ,  Y10S148/115 ,  Y10S148/122 ,  H01L2924/00

    Abstract: Disclosed are three processes, which all employ a common sequence of steps, for forming discrete and integrtated circuit transistors having emitters self-aligned between base enhancements and various polycrystalline silicon contacting members. The first process forms transistors having polycrystalline emitter contacts. The second process employs anisotropic etching techniques for forming self-aligned, integrated circuit transistors having polycrystalline emitter and collector contacts along with shallow isolation and collector buried layer contacting diffusions. The third process provides a transistor having polycrystalline silicon contacts to the emitter and base enhancement regions and utilizes boron doped polycrystalline silicon base contacts as an etch stop.

    Abstract translation: 公开了三个过程，它们都采用共同的步骤序列，用于形成离散和积分的电路晶体管，其具有在基极增强之间自对准的发射极和各种多晶硅接触构件。 第一工艺形成具有多晶发射极触点的晶体管。 第二种方法采用各向异性蚀刻技术，用于形成具有多晶发射极和集电极触点以及浅隔离和集电极掩埋层接触扩散的自对准集成电路晶体管。 第三工艺提供了具有到发射极和基极增强区域的多晶硅接触的晶体管，并且使用硼掺杂的多晶硅基极触点作为蚀刻停止。

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