公开(公告)号：US3576682A

公开(公告)日：1971-04-27

申请号：US3576682D

申请日：1968-02-05

Applicant: PHILIPS CORP

Inventor： FROUIN JEAN-CLAUDE ,  BREBISSON MICHEL DE

IPC: H01L21/761 ,  H01L21/8224 ,  H01L27/082 ,  H01L7/64

CPC classification number: H01L21/761 ,  H01L21/8224 ,  H01L27/0821

Abstract: A METHOD IS DESCRIBED OF MAKING A MONOLITHIC 1C WITH COMPLEMENTARY TRANSISTORS WHEREIN THE P-EMITTER OF THE PNP TRANSISTOR IS FIFFUSED SIMULTANEOUSLY WITH THE P-ISOLATION WALLS, FOLLOWED BY SIMULTANEOUS DIFFUSION OF THE PBASE OF THE NPN TRANSISTOR AND THE P-COLLECTOR OF THE PNP TRANSISTOR, FOLLOWED BY SIMULTANEOUS DIFFUSION OF THE NEMITTER FOR THE NPN TRANSISTOR AND THE N-CONTACT REGIONS FOR THE NPN-COLLECTOR AND THE PNP-BASE.

公开(公告)号：US3562032A

公开(公告)日：1971-02-09

申请号：US3562032D

申请日：1968-02-05

Applicant: PHILIPS CORP

Inventor： FROUIN JEAN-CLAUDE ,  BREBISSON MICHEL DE

IPC: H01L21/761 ,  H01L21/8224 ,  H01L21/8228 ,  H01L27/082 ,  H01L7/44 ,  H01L7/64

CPC classification number: H01L27/0826 ,  H01L21/761 ,  H01L21/8224 ,  H01L21/82285 ,  H01L27/0821 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/096 ,  Y10S148/151

Abstract: A METHOD FOR MAKING A MONOLITHIC INTEGRATED CIRCUIT IS DESCRIBED. THE CIRCUIT INCLUDES VERTICAL COMPLEMENTARY TRANSISTORS IN ISOLATED ISLANDS. THE EMITTER OF THE PNP TRANSISTOR IS DIFFUSED SIMULTANEOUSLY IWTH THE ISOLATION WALLS DEFINING THE ISLANDS. THE BASE OF THE PNP TRANSISTOR IS FORMED BY THE ISLAND REGION ADJACENT THE SUBSTRATE, WHICH ACTS AS A COLLECTOR. THE NPN TRANSISTOR IS THE USUAL DOUBLE-DIFFUSED TRANSISTOR.

公开(公告)号：US3607465A

公开(公告)日：1971-09-21

申请号：US3607465D

申请日：1968-06-28

Applicant: PHILIPS CORP

Inventor： FROUIN JEAN-CLAUDE

IPC: H01L21/8222 ,  H01L27/06 ,  H01L27/082 ,  H01L29/00 ,  H01L7/36

CPC classification number: H01L27/0826 ,  H01L21/8222 ,  H01L27/0652 ,  H01L29/00 ,  Y10S148/037 ,  Y10S148/085 ,  Y10S148/145 ,  Y10S148/151 ,  Y10S438/983

Abstract: A method of making in a monolithic integrated semiconductor circuit a Zener diode having a reverse breakdown voltage in the range of 2.5-6 volts is described. This is obtained by constructing one of the diode zones as a heavily doped buried layer and the other diode zone as a heavily doped surface layer and out-diffusing the former and in-diffusing the latter until they meet to form an abrupt junction having the desired characteristics. A heavily doped surface contact region is diffused down to the buried zone to make available a surface contact for the latter.

公开(公告)号：US3595714A

公开(公告)日：1971-07-27

申请号：US3595714D

申请日：1968-07-01

Applicant: PHILIPS CORP

Inventor： THIRE JACQUES ,  BREBISSON MICHEL DE ,  FROUIN JEAN-CLAUDE

IPC: H01L21/82 ,  H01L27/06 ,  H01L29/808 ,  H03F3/347 ,  H01L7/36 ,  H01L7/44

CPC classification number: H03F3/347 ,  H01L21/82 ,  H01L27/0635 ,  H01L29/808 ,  Y10S148/037 ,  Y10S148/053 ,  Y10S148/085 ,  Y10S148/145 ,  Y10S148/151

Abstract: A METHOD OF MAKIN A JUNCTION FIELD EFFECT TRANSISTOR, BY STEPS COMPATIBLE WITH THE PLANAR TECHNOLOGY IS DESCRIBED. TWO EPITAXIAL ALYERS OF THE SAME TYPE ARE DEPOSITED ON A SUBSTRATE OF THE OPPOSITE TYPE, WITH A BURIED LAYER OF THE OPPOSITE TYPE PROVIDED BETWEEN THE EPITAXIAL LAYERS. THE BURIED LAYER IS MAINTAINED SPACED FROM THE SUBSTRATE, TO DEFINE AN ISOLATION ZONE FOR THE TRANSITOR, AND SPACED FROM THE SURFACE, TO DEFINE A CHANNEL REGION OF THE ORIGINAL EPITAXIAL MATERIAL UNDERNEATH A DIFFUSED GATE ELECTRODE.

公开(公告)号：US3595713A

公开(公告)日：1971-07-27

申请号：US3595713D

申请日：1968-07-01

Applicant: PHILIPS CORP

Inventor： BREBISSON MICHEL DE ,  FROUIN JEAN-CLAUDE ,  THIRE JACQUES

IPC: H01L21/74 ,  H01L27/06 ,  H01L27/082 ,  H03F3/347 ,  H01L7/36 ,  H01L7/44

CPC classification number: H01L21/74 ,  H01L27/0635 ,  H01L27/0826 ,  H03F3/347 ,  Y10S148/037 ,  Y10S148/049 ,  Y10S148/085 ,  Y10S148/098 ,  Y10S148/145 ,  Y10S148/151

Abstract: A METHOD OF MAKING AN INTEGRATED CIRCUIT CONTAINING NPN AND COMPLEMENTARY PNP TRANSISTORS IS DESCRIBED. IN A PREFERRED ARRANGEMENT, A P SUBSTRATE WITHOUT ACTIVE BURIED LAYERS IS COVERED WITH A FIRST N EPITAXIAL LAYER IN WHICH AN N+ BURIED LAYER FOR THE NPN TRANSISTOR AND A P+ BURIED LAYER FOR THE PNP TRANSISTOR IS PROVIDED. THEN A SECOND N EPITAXIAL LAYER IS PROVIDED. THE N EMITTER AND P BASE ARE PROVIDED BY DIFFUSION OVER THE P+ BURIED LAYER, OUT THE N BASE IS CONSTITUTED BY THE SECOND EPITAXIAL LAYER. THE P COLLECTOR IS FORMED BY THE BURIED LAYER, TO WHICH A DIFFUSED CONTACT IS MADE. THE TWO BURIED LAYERS REMAIN SPACED FROM THE SUBSTRATE AND THE SURFACE. THUS, THE PNP TRANSISTOR IS ISOLATED BY THE FIRST EPITAXIAL LAYER.

公开(公告)号：US3500139A

公开(公告)日：1970-03-10

申请号：US3500139D

申请日：1968-03-18

Applicant: PHILIPS CORP

Inventor： FROUIN JEAN-CLAUDE ,  BREBISSON MICHEL DE

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L27/06 ,  H03F3/347 ,  H01L11/00 ,  H01L5/00 ,  H01L15/00

CPC classification number: H03F3/347 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0647 ,  Y10S148/036 ,  Y10S148/043 ,  Y10S148/049 ,  Y10S148/05 ,  Y10S148/085 ,  Y10S148/122