公开(公告)号：US5401686A

公开(公告)日：1995-03-28

申请号：US909600

申请日：1992-07-07

申请人： Hiromi Kiyose

发明人： Hiromi Kiyose

IPC分类号： H01L21/22 ,  C30B31/12 ,  D21H27/00 ,  H01L21/223

CPC分类号： C30B31/12 ,  H01L21/223 ,  Y10S148/038

摘要： The temperature of the front heater is set to a higher value than the set temperature of the center heater and the temperature of the rear heater is set to a lower value than the set temperature of the center heater to thereby provide such a temperature gradient that the temperature of a center heater region gradually rises from the rear side toward the front side and the impurity diffusion is accelerated under the temperature gradient, whereby it is possible to compensate for the decrease in the quantity of the diffused impurity caused by the lowering of the impurity concentration of the impurity gas gradually from the rear side toward the front side, so that the impurity is uniformly diffused into the wafers located in the core pipe.

摘要翻译： 前加热器的温度被设定为比中心加热器的设定温度更高的值，并且后加热器的温度被设定为比中心加热器的设定温度低的值，从而提供这样的温度梯度，使得 中心加热器区域的温度从后侧朝向前侧逐渐上升，并且在温度梯度下杂质扩散加速，由此可以补偿由于杂质的降低引起的扩散杂质的量的减少 杂质气体从后侧朝向前侧逐渐浓缩，从而杂质均匀地扩散到位于芯管中的晶片中。

公开(公告)号：US4125426A

公开(公告)日：1978-11-14

申请号：US825763

申请日：1977-08-18

申请人： Katsuyuki Inayoshi ,  Yoshinobu Monma

发明人： Katsuyuki Inayoshi ,  Yoshinobu Monma

IPC分类号： H01L29/73 ,  H01L21/00 ,  H01L21/225 ,  H01L21/28 ,  H01L21/285 ,  H01L21/316 ,  H01L21/331 ,  H01L21/768 ,  H01L21/8222 ,  H01L21/312

CPC分类号： H01L21/8222 ,  H01L21/00 ,  H01L21/2257 ,  H01L21/28525 ,  H01L21/316 ,  H01L21/768 ,  Y10S148/038 ,  Y10S148/106 ,  Y10S148/123 ,  Y10S148/138 ,  Y10S438/923

摘要： A simplified method of manufacturing a semiconductor device is disclosed wherein a base region is formed on a silicon substrate and an impurity is diffused into the base region. Any insulating film present on the silcon substrate is removed, substrate and an even film of silicon dioxide is coated thereon. Emitter diffusion windows, base electrode windows, collector electrode windows and resistor electrode windows are formed in the silicon dioxide film and a uniform film of polycrystal silicon is deposited over the silicon dioxide film and the electrode windows. Impurities are diffused through the polycrystal silicon film at the emitter and collector windows but not through the base window. An aluminum electrode layer is formed on the polycrystal silicon layer and patterned to form an electrode wiring pattern. Subsequently, the polysilicon layer is removed in exposed areas utilizing the aluminum electrode layer as a mask.

摘要翻译： 公开了一种制造半导体器件的简化方法，其中在硅衬底上形成基极区域，并且杂质扩散到基极区域中。 去除存在于硅氧烷衬底上的任何绝缘膜，将基底和均匀的二氧化硅膜涂覆在其上。 在二氧化硅膜中形成发射极扩散窗，基极窗，集电极电极窗和电阻电极窗，并在二氧化硅膜和电极窗上沉积均匀的多晶硅膜。 杂质通过多晶硅膜在发射极和收集器窗口扩散，但不通过基底窗口扩散。 在多晶硅层上形成铝电极层并图案化以形成电极布线图案。 随后，利用铝电极层作为掩模，在曝光区域中去除多晶硅层。

公开(公告)号：US3969748A

公开(公告)日：1976-07-13

申请号：US475179

申请日：1974-05-31

申请人： Noboru Horie ,  Kazuo Hoya

发明人： Noboru Horie ,  Kazuo Hoya

IPC分类号： H01L21/8222 ,  H01L21/331 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/73 ,  H01L29/735 ,  H01L27/02 ,  H01L27/04 ,  H01L29/72

CPC分类号： H01L27/0821 ,  H01L27/0825 ,  H01L29/735 ,  Y10S148/02 ,  Y10S148/038 ,  Y10S148/085 ,  Y10S148/096 ,  Y10S148/136 ,  Y10S148/151 ,  Y10S257/914

摘要： A multiple transistor consists of vertical and lateral transistors, the collector region of the lateral transistor is formed by diffusion within the diffused base region of the vertical transistor simultaneously with the emitter region of the vertical transistor, into a structure in which the base of the vertical transistor and the collector of the lateral transistor are short-circuited. As a result the current gain of the lateral transistor can be varied by changing the area of the collector region.

摘要翻译： 多晶体管由垂直和横向晶体管构成，横向晶体管的集电极区域由与垂直晶体管的发射极区同时垂直晶体管的扩散基极区域内的扩散形成为垂直晶体管的基极的结构 晶体管和横向晶体管的集电极短路。 结果，可以通过改变集电极区域的面积来改变横向晶体管的电流增益。

公开(公告)号：US3667006A

公开(公告)日：1972-05-30

申请号：US3667006D

申请日：1970-02-19

申请人： PHILIPS CORP

发明人： RUEGG HENIZ WALTER

IPC分类号： H01L21/00 ,  H01L21/74 ,  H01L27/00 ,  H01L27/082 ,  H01L11/06

CPC分类号： H01L27/0821 ,  H01L21/00 ,  H01L21/74 ,  H01L27/00 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/085 ,  Y10S148/096 ,  Y10S148/145 ,  Y10S148/151

摘要： The invention relates to a semiconductor device having a substrate of the one conductivity type on which an epitaxial layer divided into islands of the opposite conductivity type is provided and in which at least one island comprises a lateral transistor and a buried layer of the opposite conductivity type. In order to obtain both a small vertical emitter injection and a high collector-base breakdown voltage, the emitter zone has a larger thickness than the collector zone and, in contrast with the collector zone, the emitter zone reaches up to the buried layer. No additional manufacturing step is necessary for the manufacture.

摘要翻译： 本发明涉及一种具有一种导电类型的衬底的半导体器件，在该衬底上设置有分为相反导电类型的岛的外延层，其中至少一个岛包括横向晶体管和相反导电类型的掩埋层 。 为了获得小的垂直发射体注入和高的集电极 - 基极击穿电压，发射极区域具有比集电极区域更大的厚度，并且与集电极区域相反，发射极区域直到埋层。 不需要额外的制造步骤来制造。

公开(公告)号：US4965220A

公开(公告)日：1990-10-23

申请号：US306393

申请日：1989-02-06

申请人： Hiroshi Iwasaki

发明人： Hiroshi Iwasaki

IPC分类号： H01L21/76 ,  H01L21/225 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732

CPC分类号： H01L21/2257 ,  H01L21/8249 ,  H01L27/0623 ,  Y10S148/01 ,  Y10S148/032 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/082 ,  Y10S148/123 ,  Y10S148/124

摘要： A semiconductor integrated circuit device is disclosed which comprises a bipolar transistor and a field effect transistor, in which a gate electrode of the field effect transistor and a collector electrode of the bipolar transistor are formed from a common electrode layer of a high impurity concentration, and in which the collector region of the bipolar transistor comprises a region of a high impurity concentration having a conductivity type the same as that of the collector region of the bipolar transistor.

公开(公告)号：US4780425A

公开(公告)日：1988-10-25

申请号：US119668

申请日：1987-11-12

申请人： Teruo Tabata

发明人： Teruo Tabata

IPC分类号： H01L21/74 ,  H01L21/8222 ,  H01L21/8228 ,  H01L29/732 ,  H01L21/20 ,  H01L27/04

CPC分类号： H01L29/7322 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/82285 ,  Y10S148/011 ,  Y10S148/035 ,  Y10S148/038

摘要： The present invention relates to a semiconductor device and a method of producing the same. According to this method, a lower diffusion layer of a double isolation diffusion area is attached to a surface of a substrate, an epitaxial layer being formed on the lower diffusion layer, the lower diffusion layer being largely outdiffused upwardly in the epitaxial layer and simultaneously an element diffusion area being deeply diffused from a surface of the epitaxial layer, and then an upper diffusion layer of the double isolation diffusion area being shallowly diffused from the surface of the epitaxial layer. Thus, the lateral expansion of the upper diffusion layer of the double isolation diffusion area can be suppressed and the integrated extent can be improved. On the other hand, in a semiconductor device of the present invention, the above described double isolation diffusion area is formed and a collector area, a base area and an emitter area are formed all over the width of the epitaxial layer (the base area and the emitter area are formed by a double diffusion). In addition, it includes a vertical type transistor whose fluctuation of a width of the base area is reduced, so that the transition frequency f.sub.T and current gain h.sub.FE of this transistor are increased.

摘要翻译： 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 根据该方法，将双重隔离扩散区域的下部扩散层附着在基板的表面，外延层形成在下部扩散层上，下部扩散层在外延层中大大向外扩散，同时 元件扩散区域从外延层的表面深度扩散，然后双重隔离扩散区域的上扩散层从外延层的表面浅扩散。 因此，可以抑制双重隔离扩散区域的上扩散层的横向膨胀，并且可以提高一体化程度。 另一方面，在本发明的半导体装置中，形成上述双重隔离扩散区域，并且在外延层的整个宽度（基底面积和宽度）上形成集电极区域，基极区域和发射极区域 发射极区域由双扩散形成）。 此外，它包括垂直型晶体管，其基极区域的宽度的波动减小，使得该晶体管的跃迁频率fT和电流增益hFE增加。

公开(公告)号：US4144106A

公开(公告)日：1979-03-13

申请号：US820319

申请日：1977-07-29

申请人： Hiromitsu Takeuchi

发明人： Hiromitsu Takeuchi

IPC分类号： H01L27/082 ,  H01L21/22 ,  H01L21/225 ,  H01L21/285 ,  H01L21/331 ,  H01L21/8226 ,  H01L29/73 ,  H01L21/20

CPC分类号： H01L21/28525 ,  H01L21/2257 ,  H01L21/8226 ,  Y10S148/038 ,  Y10S148/087 ,  Y10S148/106 ,  Y10S148/122 ,  Y10S148/151 ,  Y10S148/167

摘要： During the manufacture of an I.sup.2 L device, to achieve diffusion steps for a collector region and a collar region at the same time, polycrystal silicon is deposited over the whole surface of the collector region and then an impurity is diffused simultaneously into the collector region and the collar region.

摘要翻译： 在制造I2L器件期间，为了同时实现集电极区域和套环区域的扩散步骤，多晶硅沉积在集电极区域的整个表面上，然后杂质同时扩散到集电极区域，并且 领地区。

公开(公告)号：US3884732A

公开(公告)日：1975-05-20

申请号：US39804073

申请日：1973-09-17

申请人： IBM

发明人： BAITINGER UTZ G ,  NAJMANN KNUT K

IPC分类号： G11C11/411 ,  H01L27/102 ,  H01L29/10 ,  H01L7/44 ,  H01L7/64 ,  H01L29/72

CPC分类号： H01L29/1004 ,  G11C11/4116 ,  H01L27/1025 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/085 ,  Y10S148/145 ,  Y10S148/151

摘要： A monolithic storage matrix having cells formed of multi-emitter transistors in which one emitter of each transistor forms part of the storage circuit and the other emitter of each transistor is coupled to the accessing and retrieval circuits. The transistors portions for storage are formed with bases of a given width and the transistors portions coupled to the accessing and retrieving circuits have a lesser width so that short access times are obtained while the stability of the storage circuit is maintained.

公开(公告)号：US3735481A

公开(公告)日：1973-05-29

申请号：US3735481D

申请日：1971-02-25

申请人： HITACHI LTD

发明人： MAKIMOTO T

IPC分类号： H01L27/00 ,  H01L27/06 ,  H01L29/08 ,  B01J17/00

CPC分类号： H01L29/0821 ,  H01L27/00 ,  H01L27/0652 ,  Y10S148/037 ,  Y10S148/038 ,  Y10S148/085

摘要： A method of manufacturing a semiconductor integrated circuit in which a P type semiconductor layer is epitaxially grown in the surface of a P type semiconductor substrate containing N buried layers therein, the P type layer is divided into a plurality of electrically isolated portions by N type regions which are formed by diffusing a donor impurity into the surface of said P type semiconductor layer towards the N type buried layers, the divided P type semiconductor portions forming individually diodes and transistors with the N type regions connected to said buried layers as their structural elements.

摘要翻译： 一种制造半导体集成电路的方法，其中P型半导体层在其中包含N +掩埋层的P型半导体衬底的表面中外延生长，P型层被分成多个电隔离部分 N +型区域，其通过将施主杂质扩散到所述P型半导体层的表面朝向N +型掩埋层而形成，分割的P型半导体部分分别形成二极管和具有N + 连接到所述埋层的类型区域作为其结构元件。

公开(公告)号：US5801087A

公开(公告)日：1998-09-01

申请号：US582310

申请日：1996-01-03

申请人： Monte Manning ,  Shubneesh Batra ,  Charles H. Dennison

发明人： Monte Manning ,  Shubneesh Batra ,  Charles H. Dennison

IPC分类号： H01L21/285 ,  H01L21/225 ,  H01L21/28

CPC分类号： H01L21/28525 ,  Y10S148/038 ,  Y10S148/123

摘要： The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

摘要翻译： 本发明的方法引入了一种在半导体器件中的支撑衬底上形成导电掺杂触点的方法，其使导电掺杂剂的侧向向外扩散最小化，并且还通过以下步骤提供低电阻接触：制备导电区域 接受接触形成; 在所述导电区域上形成磷原位掺杂多晶硅层; 在磷原位掺杂多晶硅层上形成砷原位掺杂的多晶硅层，其中两个本征掺杂的多晶硅层在不同的沉积步骤中依次沉积; 并在约900℃-1100℃的温度范围内对层进行退火，从而进行足够的热处理以使磷原子分解形成在导电区域和磷原位掺杂多晶硅层之间的第一界面二氧化硅层。