公开(公告)号：US09673096B2

公开(公告)日：2017-06-06

申请号：US14541239

申请日：2014-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Joachim Hirschler ,  Michael Roesner ,  Markus Juch Heinrici ,  Gudrun Stranzl ,  Martin Mischitz ,  Martin Zgaga

IPC: H01L21/78 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/6835 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/03002 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03505 ,  H01L2224/03848 ,  H01L2224/039 ,  H01L2224/05794 ,  H01L2224/05847 ,  H01L2224/06181 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2221/68381

Abstract: According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.

公开(公告)号：US20140231981A1

公开(公告)日：2014-08-21

申请号：US14347177

申请日：2013-01-10

Applicant: Panasonic Corporation

Inventor： Toshiyuki Kojima ,  Tsukasa Shiraishi ,  Norihito Tsukahara ,  Takayuki Hirose ,  Keiko Ikuta ,  Masayoshi Koyama

IPC: H01L23/36 ,  H01L21/48

CPC classification number: H01L23/36 ,  H01L21/4875 ,  H01L23/051 ,  H01L23/24 ,  H01L23/4006 ,  H01L23/4093 ,  H01L23/492 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/72 ,  H01L2224/03003 ,  H01L2224/03005 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: A semiconductor device (1) includes: a semiconductor chip (2) having a first main surface and a second main surface opposite to the first main surface; a heat dissipating plate (3) opposed to the first main surface; a first electrode (5) disposed between the first main surface and the heat dissipating plate (3) so as to be electrically connected to the semiconductor chip (2); a pressure contact member (4) opposed to the second main surface; a second electrode (6) disposed between the second main surface and the pressure contact member (4) so as to be electrically connected to the semiconductor chip (2); and a pressure generating mechanism that generates a pressure for pressing the first electrode (5) into contact with the heat dissipating plate (3) and the semiconductor chip (2) and pressing the second electrode (6) into contact with the pressure contact member (4) and the semiconductor chip (2).

Abstract translation: 半导体器件（1）包括：具有第一主表面和与第一主表面相对的第二主表面的半导体芯片（2） 与第一主表面相对的散热板（3）; 设置在所述第一主表面和所述散热板之间以与半导体芯片（2）电连接的第一电极（5）; 与第二主表面相对的压接部件（4）; 设置在第二主表面和压接元件之间以与半导体芯片（2）电连接的第二电极（6）; 以及压力产生机构，其产生用于按压所述第一电极（5）的压力与所述散热板（3）和所述半导体芯片（2）接触并且将所述第二电极（6）按压到所述压接部件（ 4）和半导体芯片（2）。

公开(公告)号：US20240006421A1

公开(公告)日：2024-01-04

申请号：US18091322

申请日：2022-12-29

Applicant: HKC CORPORATION LIMITED

Inventor： ZHONGXIE XU ,  HAOXUAN ZHENG

IPC: H01L27/12 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L27/1244 ,  H01L25/167 ,  H01L27/1288 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/06 ,  H01L2224/02255 ,  H01L2224/03005 ,  H01L2224/0347 ,  H01L2224/05573 ,  H01L2224/05552 ,  H01L2224/06132 ,  H01L2224/08145 ,  H01L2924/12041

Abstract: Disclosed is a method for preparing a display substrate, including: providing a driving substrate; wherein the driving substrate includes: a base substrate; a pixel driving circuit layer; a first pad and a second pad, spaced from each other, and connected to the pixel driving circuit layer; and an electrostatic protection alignment, spaced from the first pad; and transferring a light-emitting element to the driving substrate, such that an anode of the light-emitting element is connected in alignment with the first pad and a cathode of the light emitting-element is connected in alignment with the second pad. The first pad includes a first toothed tip arranged on a side of the first pad facing the electrostatic protection alignment, and the electrostatic protection alignment includes a second toothed tip arranged on a side of the electrostatic protection alignment facing the first pad.

公开(公告)号：US20160329288A1

公开(公告)日：2016-11-10

申请号：US15215037

申请日：2016-07-20

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： SHEILA F. CHOPIN ,  MIN DING ,  VARUGHESE MATHEW ,  SCOTT S. ROTH

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/03015 ,  H01L2224/03019 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05565 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

Abstract translation: 通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极 在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。

公开(公告)号：US20230223369A1

公开(公告)日：2023-07-13

申请号：US17661375

申请日：2022-04-29

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.

Inventor： Zengyan FAN

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L2224/0612 ,  H01L2224/1162 ,  H01L2224/03005 ,  H01L2224/14104

Abstract: The present application provides a semiconductor structure and a forming method thereof. The method of forming the semiconductor structure includes: providing a semiconductor chip and a substrate; forming, on the substrate, a first covering film covering a metal pad and a surface of the substrate, a plurality of up-narrow and down-wide openings being formed in the first covering film, and a bottom of each of the up-narrow and down-wide openings correspondingly exposing a surface of the metal pad; and flipping the semiconductor chip onto the substrate, such that a solder bump on a metal pillar is correspondingly located in the up-narrow and down-wide opening, and the solder bump fill the up-narrow and down-wide opening.

公开(公告)号：US20160141208A1

公开(公告)日：2016-05-19

申请号：US14541239

申请日：2014-11-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Hirschler Joachim ,  Roesner Michael ,  Heinrici Juch Markus ,  Stranzl Gudrun ,  Mischitz Martin ,  Zgaga Martin

IPC: H01L21/78 ,  H01L21/324 ,  H01L23/29 ,  H01L21/3213

CPC classification number: H01L21/78 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/6835 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/94 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/03002 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03464 ,  H01L2224/03505 ,  H01L2224/03848 ,  H01L2224/039 ,  H01L2224/05794 ,  H01L2224/05847 ,  H01L2224/06181 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2221/68381

Abstract: According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.

Abstract translation: 根据各种实施例，用于处理半导体衬底的方法可以包括：用金属覆盖半导体衬底的多个管芯区域; 从所述半导体衬底形成多个管芯，其中所述多个管芯中的每个管芯被所述金属覆盖; 并且随后对所述多个管芯中的至少一个管芯进行金属覆盖退火。

公开(公告)号：US09076752B2

公开(公告)日：2015-07-07

申请号：US14347177

申请日：2013-01-10

Applicant: Panasonic Corporation

Inventor： Toshiyuki Kojima ,  Tsukasa Shiraishi ,  Norihito Tsukahara ,  Takayuki Hirose ,  Keiko Ikuta ,  Masayoshi Koyama

IPC: H01L23/48 ,  H01L23/34 ,  H01L23/10 ,  H01L23/36 ,  H01L23/40 ,  H01L23/492 ,  H01L23/051 ,  H01L23/00 ,  H01L21/48 ,  H01L23/24

CPC classification number: H01L23/36 ,  H01L21/4875 ,  H01L23/051 ,  H01L23/24 ,  H01L23/4006 ,  H01L23/4093 ,  H01L23/492 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/72 ,  H01L2224/03003 ,  H01L2224/03005 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599

Abstract: A semiconductor device (1) includes: a semiconductor chip (2) having a first main surface and a second main surface opposite to the first main surface; a heat dissipating plate (3) opposed to the first main surface; a first electrode (5) disposed between the first main surface and the heat dissipating plate (3) so as to be electrically connected to the semiconductor chip (2); a pressure contact member (4) opposed to the second main surface; a second electrode (6) disposed between the second main surface and the pressure contact member (4) so as to be electrically connected to the semiconductor chip (2); and a pressure generating mechanism that generates a pressure for pressing the first electrode (5) into contact with the heat dissipating plate (3) and the semiconductor chip (2) and pressing the second electrode (6) into contact with the pressure contact member (4) and the semiconductor chip (2).

Abstract translation: 半导体器件（1）包括：具有第一主表面和与第一主表面相对的第二主表面的半导体芯片（2） 与第一主表面相对的散热板（3）; 设置在所述第一主表面和所述散热板之间以与半导体芯片（2）电连接的第一电极（5）; 与第二主表面相对的压接部件（4）; 设置在第二主表面和压接元件之间以与半导体芯片（2）电连接的第二电极（6）; 以及压力产生机构，其产生用于按压所述第一电极（5）的压力与所述散热板（3）和所述半导体芯片（2）接触并且将所述第二电极（6）按压到所述压力接触部件（ 4）和半导体芯片（2）。

公开(公告)号：US11876061B2

公开(公告)日：2024-01-16

申请号：US17420586

申请日：2019-03-06

Applicant: Mitsubishi Electric Corporation

Inventor： Yasuki Aihara

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/04 ,  H01L24/48 ,  H01L2224/03005 ,  H01L2224/039 ,  H01L2224/03462 ,  H01L2224/03466 ,  H01L2224/03632 ,  H01L2224/04042 ,  H01L2224/05016 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2924/10335 ,  H01L2924/30105

Abstract: Provided here are: an electrically-conductive semiconductor substrate with which a semiconductor circuit is formed; an insulating film deposited on a major surface of the electrically-conductive semi-conductor substrate; and a bonding pad having fixing parts fixed onto the insulating film, side wall parts rising up from the fixing parts, and an electrode part connected to the side wall parts and disposed in parallel to the major surface; wherein the electrode part forms, together with the insulating film, a gap region therebetween, and portions of the electrode part where it is connected to the side wall parts are configured to have at least one of: a positional relationship in which they sandwich therebetween a central portion of the electrode part in its bonding region to be bonded to a bonding wire; and a positional relationship in which they surround the central portion.

公开(公告)号：US09412709B2

公开(公告)日：2016-08-09

申请号：US13898949

申请日：2013-05-21

Applicant: Sheila F. Chopin ,  Min Ding ,  Varughese Mathew ,  Scott S. Roth

Inventor： Sheila F. Chopin ,  Min Ding ,  Varughese Mathew ,  Scott S. Roth

IPC: H01L21/56 ,  H01L21/44 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/02 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/03015 ,  H01L2224/03019 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05565 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

Abstract translation: 通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极 在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。

公开(公告)号：US20140346663A1

公开(公告)日：2014-11-27

申请号：US13898949

申请日：2013-05-21

Applicant: Sheila F. Chopin ,  Min Ding ,  Varughese Mathew ,  Scott S. Roth

Inventor： Sheila F. Chopin ,  Min Ding ,  Varughese Mathew ,  Scott S. Roth

IPC: H01L23/00

CPC classification number: H01L24/02 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/03005 ,  H01L2224/03009 ,  H01L2224/03015 ,  H01L2224/03019 ,  H01L2224/034 ,  H01L2224/03622 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05 ,  H01L2224/05565 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48824 ,  H01L2224/73265 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/365 ,  H01L2924/3651 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.

Abstract translation: 通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极 在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。