公开(公告)号：US20190308274A1

公开(公告)日：2019-10-10

申请号：US16374265

申请日：2019-04-03

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Markus Menath ,  Gudrun Stranzl

IPC: B23K26/362 ,  B23K26/40 ,  H01L21/67 ,  H01L21/3065 ,  H01L29/16

Abstract: A method of processing silicon carbide containing crystalline substrate is provided. The method includes pyrolyzing a surface of the silicon carbide containing crystalline substrate to produce a silicon and carbon containing debris layer over the silicon carbide containing crystalline substrate, and removing the silicon and carbon containing debris layer, wherein the pyrolyzing and the removing is repeated at least once.

公开(公告)号：US20190295981A1

公开(公告)日：2019-09-26

申请号：US16360570

申请日：2019-03-21

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Markus Menath ,  Gudrun Stranzl

IPC: H01L23/00 ,  H01L29/16 ,  H01L29/45 ,  H01L21/04

Abstract: A semiconductor device includes a silicon carbide layer, a metal carbide layer arranged over the silicon carbide layer, and a solder layer arranged over and in contact with the metal carbide layer.

公开(公告)号：US10005659B2

公开(公告)日：2018-06-26

申请号：US15440962

申请日：2017-02-23

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Ursula Hedenig ,  Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga

IPC: B81B7/00 ,  B01D67/00 ,  B81C1/00

CPC classification number: B81B7/0061 ,  B01D67/0034 ,  B81B2201/0257 ,  B81B2201/10 ,  B81C1/00904 ,  B81C2201/0132 ,  Y10T428/24273

Abstract: A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.

公开(公告)号：US20170194205A1

公开(公告)日：2017-07-06

申请号：US14979200

申请日：2015-12-22

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

公开(公告)号：US09496193B1

公开(公告)日：2016-11-15

申请号：US14858633

申请日：2015-09-18

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga ,  Martin Sporn ,  Tobias Schmidt

IPC: H01L23/04 ,  H01L21/48 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/12 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L21/4803 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3185 ,  H01L23/4827 ,  H01L24/05 ,  H01L24/26 ,  H01L24/29 ,  H01L24/83 ,  H01L24/94 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04026 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05644 ,  H01L2224/05687 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32245 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/0105 ,  H01L2924/053 ,  H01L2924/049

Abstract: A semiconductor chip includes a body having a frontside, a backside opposite the frontside, and sidewalls extending between the backside and frontside, at least a portion of each sidewall having a defined surface structure with hydrophobic characteristics to inhibit travel of a bonding material along the sidewalls during attachment of the semiconductor chip to a carrier with the bonding material.

Abstract translation: 半导体芯片包括具有前侧的主体，与前侧相对的后侧，以及在后侧和前侧之间延伸的侧壁，每个侧壁的至少一部分具有限定的具有疏水特性的表面结构，以阻止接合材料沿着侧壁移动 在使用所述接合材料将半导体芯片附接到载体的过程中。

公开(公告)号：US09293371B2

公开(公告)日：2016-03-22

申请号：US14748260

申请日：2015-06-24

Applicant: Infineon Technologies AG

Inventor： Anja Reitmeier ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

公开(公告)号：US20150294911A1

公开(公告)日：2015-10-15

申请号：US14748260

申请日：2015-06-24

Applicant: Infineon Technologies AG

Inventor： Anja Reitmeier ,  Hermann Wendt ,  Thomas Fischer ,  Bernhard Weidgans ,  Gudrun Stranzl ,  Tobias Schmidt ,  Dietrich Bonart

IPC: H01L21/78 ,  H01L21/768 ,  H01L21/285 ,  H01L21/3213

CPC classification number: H01L21/78 ,  H01L21/28568 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/76841 ,  H01L21/76892

Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.

Abstract translation: 提供了一种用于处理半导体工件的方法，其可以包括：提供包括设置在半导体工件侧面的金属化层堆叠的半导体工件，金属化层堆叠包括至少第一层和设置在第一层上的第二层 层，其中所述第一层包含第一材料，并且所述第二层包含不同于所述第一材料的第二材料; 图案化金属化层堆叠，其中图案化金属化层堆叠包括通过蚀刻溶液湿法蚀刻第一层和第二层，蚀刻溶液对于第一材料和第二材料具有至少基本上相同的蚀刻速率。

公开(公告)号：US20150279740A1

公开(公告)日：2015-10-01

申请号：US14226666

申请日：2014-03-26

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Manfred Engelhardt ,  Johann Schmid ,  Gudrun Stranzl ,  Joachim Hirschler

IPC: H01L21/78 ,  H01L21/768

CPC classification number: H01L21/7806 ,  H01L21/02057 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/76879 ,  H01L21/76898 ,  H01L21/78 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/10157 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an adhesive component and forming a through trench through the substrate to expose the adhesive component. At least a portion of the adhesive component is etched and a metal layer is formed over sidewalls of the through trench.

Abstract translation: 根据本发明的实施例，一种形成半导体器件的方法包括：使用粘合剂组件将衬底附着到载体上，并通过衬底形成通孔以暴露粘合剂组分。 蚀刻粘合剂组分的至少一部分，并且在通孔的侧壁上形成金属层。

公开(公告)号：US20150206802A1

公开(公告)日：2015-07-23

申请号：US14158398

申请日：2014-01-17

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Schneegans

IPC: H01L21/78 ,  H01L21/66 ,  H01L23/00

CPC classification number: H01L21/78 ,  B23H1/00 ,  B23H9/00 ,  H01L22/10 ,  H01L22/34 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of separating individual dies of a semiconductor wafer includes forming a metal layer on a first surface of a semiconductor wafer, the semiconductor wafer including a plurality of dies, separating the plurality of dies from one another, and electrical discharge machining the metal layer into individual segments each of which remains attached to one of the dies. A corresponding semiconductor die produced by such a method is also provided.

Abstract translation: 分离半导体晶片的各个管芯的方法包括在半导体晶片的第一表面上形成金属层，所述半导体晶片包括多个管芯，将多个管芯彼此分离，并将金属层进行放电加工成 各个片段保持附着于一个模具。 还提供了通过这种方法制造的相应的半导体管芯。

公开(公告)号：US20190355691A1

公开(公告)日：2019-11-21

申请号：US16413195

申请日：2019-05-15

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl

IPC: H01L23/00 ,  H01L29/45

Abstract: A semiconductor device includes a silicon layer, a metal silicide layer arranged directly on the silicon layer, and a solder layer arranged directly on the metal silicide layer.