公开(公告)号：US10005659B2

公开(公告)日：2018-06-26

申请号：US15440962

申请日：2017-02-23

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Ursula Hedenig ,  Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga

IPC: B81B7/00 ,  B01D67/00 ,  B81C1/00

CPC classification number: B81B7/0061 ,  B01D67/0034 ,  B81B2201/0257 ,  B81B2201/10 ,  B81C1/00904 ,  B81C2201/0132 ,  Y10T428/24273

Abstract: A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.

公开(公告)号：US20170194205A1

公开(公告)日：2017-07-06

申请号：US14979200

申请日：2015-12-22

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

公开(公告)号：US09496193B1

公开(公告)日：2016-11-15

申请号：US14858633

申请日：2015-09-18

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga ,  Martin Sporn ,  Tobias Schmidt

IPC: H01L23/04 ,  H01L21/48 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L23/12 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L21/4803 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3185 ,  H01L23/4827 ,  H01L24/05 ,  H01L24/26 ,  H01L24/29 ,  H01L24/83 ,  H01L24/94 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/04026 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05644 ,  H01L2224/05687 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/291 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32245 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/94 ,  H01L2924/10156 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/0105 ,  H01L2924/053 ,  H01L2924/049

Abstract: A semiconductor chip includes a body having a frontside, a backside opposite the frontside, and sidewalls extending between the backside and frontside, at least a portion of each sidewall having a defined surface structure with hydrophobic characteristics to inhibit travel of a bonding material along the sidewalls during attachment of the semiconductor chip to a carrier with the bonding material.

Abstract translation: 半导体芯片包括具有前侧的主体，与前侧相对的后侧，以及在后侧和前侧之间延伸的侧壁，每个侧壁的至少一部分具有限定的具有疏水特性的表面结构，以阻止接合材料沿着侧壁移动 在使用所述接合材料将半导体芯片附接到载体的过程中。

公开(公告)号：US09741618B2

公开(公告)日：2017-08-22

申请号：US14979200

申请日：2015-12-22

Applicant: Infineon Technologies AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

公开(公告)号：US09708182B2

公开(公告)日：2017-07-18

申请号：US14838988

申请日：2015-08-28

Applicant: Infineon Technologies AG

Inventor： Andreas Behrendt ,  Kai-Alexander Schreiber ,  Sokratis Sgouridis ,  Martin Zgaga ,  Bernhard Winkler

IPC: H01L21/00 ,  B81C1/00 ,  B81B3/00 ,  H01L21/3063

CPC classification number: B81C1/00531 ,  B81B3/0021 ,  B81B3/0094 ,  B81B2203/033 ,  B81C1/00619 ,  B81C1/00626 ,  B81C2201/0139 ,  H01L21/3063

Abstract: A method for producing at least one cavity within a semiconductor substrate includes dry etching the semiconductor substrate from a surface of the semiconductor substrate at at least one intended cavity location in order to obtain at least one provisional cavity. The method includes depositing a protective material with regard to a subsequent wet-etching process at the surface of the semiconductor substrate and at cavity surfaces of the at least one provisional cavity. Furthermore, the method includes removing the protective material at least at a section of a bottom of the at least one provisional cavity in order to expose the semiconductor substrate. This is followed by electrochemically etching the semiconductor substrate at the exposed section of the bottom of the at least one provisional cavity. A method for producing a micromechanical sensor system in which this type of cavity formation is used and a corresponding MEMS are also disclosed.

公开(公告)号：US20150217997A1

公开(公告)日：2015-08-06

申请号：US14170187

申请日：2014-01-31

Applicant: Infineon Technologies AG

Inventor： Thomas Grille ,  Ursula Hedenig ,  Michael Roesner ,  Gudrun Stranzl ,  Martin Zgaga

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81B7/0061 ,  B01D67/0034 ,  B81B2201/0257 ,  B81B2201/10 ,  B81C1/00904 ,  B81C2201/0132 ,  Y10T428/24273

Abstract: A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.

Abstract translation: 公开了一种用于构造衬底和结构化衬底的方法。 在一个实施方案中，一种方法包括提供具有第一主表面和第二主表面的基底，其中所述基底固定到第二主表面处的载体布置，在所述基底的第一主表面处执行光刻步骤以标记 在第一主表面处的多个位置，对应于未来穿孔结构的多个部位以及从基板获得的多个未来单个半导体芯片的未来切割区域，以及在多个位置等离子体蚀刻基板，直到载体 从而在多个单独的半导体芯片内形成穿孔结构，同时沿着切口区分离各个半导体芯片。

公开(公告)号：US09006109B2

公开(公告)日：2015-04-14

申请号：US13851691

申请日：2013-03-27

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: H01L21/311 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: A method includes a step of performing a time multiplexed etching process, wherein the last etching step of the time multiplexed etching process is of a first time duration. After performing the time multiplexed etching process, an etching step having a second time duration is performed, wherein the second time duration is greater than the first time duration.

Abstract translation: 一种方法包括执行时间复用蚀刻工艺的步骤，其中时间复用蚀刻工艺的最后一个蚀刻步骤是第一持续时间。 在执行时间复用蚀刻处理之后，执行具有第二持续时间的蚀刻步骤，其中第二持续时间大于第一持续时间。

公开(公告)号：US20140235035A1

公开(公告)日：2014-08-21

申请号：US14260903

申请日：2014-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gudrun Stranzl ,  Martin Zgaga ,  Markus Kahn ,  Guenter Denifl

IPC: H01L21/78

CPC classification number: H01L21/78 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/82 ,  H01L21/8258

Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.

Abstract translation: 在一个实施例中，形成半导体器件的方法包括在衬底中形成开口。 该方法包括在开口内形成虚拟填充材料并使衬底变薄以暴露虚拟填充材料。 去除虚拟填充材料。

公开(公告)号：US20180315713A1

公开(公告)日：2018-11-01

申请号：US16029934

申请日：2018-07-09

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Engelhardt ,  Martin Zgaga

IPC: H01L23/544 ,  H01L21/78 ,  H01L21/3065

Abstract: An integrated circuit substrate and a method for manufacturing the same are disclosed. In an embodiment a method includes providing a wafer having a plurality of active areas, each active area being provided in a separate die area and for each active area, providing a code pattern outside the active area, the code pattern being associated with the die area.

公开(公告)号：US10020264B2

公开(公告)日：2018-07-10

申请号：US14698639

申请日：2015-04-28

Applicant: Infineon Technologies AG

Inventor： Michael Roesner ,  Gudrun Stranzl ,  Manfred Engelhardt ,  Martin Zgaga

IPC: H01L23/544 ,  H01L21/67 ,  H01L21/78 ,  H01L21/3065 ,  G06K7/14

CPC classification number: H01L23/544 ,  H01L21/30655 ,  H01L21/78 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/5446 ,  H01L2223/54473

Abstract: The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.