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    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240347087A1

    公开(公告)日：2024-10-17

    申请号：US18754823

    申请日：2024-06-26

    申请人： KIOXIA CORPORATION

    发明人： Zhao LU ,  Yuji NAGAI ,  Akio SUGAHARA ,  Takehisa KUROSAWA ,  Masaru KOYANAGI

    IPC分类号： G11C7/22 ,  G11C7/08 ,  G11C7/10

    CPC分类号： G11C7/222 ,  G11C7/08 ,  G11C7/1063 ,  G11C7/109

    摘要： A semiconductor memory device includes: first pad transmitting and receiving first timing signal; second pad transmitting and receiving data signal in response to the first timing signal; third pad receiving second timing signal; fourth pad receiving control information in response to the second timing signal; memory cell array; sense amplifier connected to the memory cell array; first register connected to the sense amplifier; second register storing first control information; third register storing second control information; and control circuit executing data-out operation. The first control information is stored in the second register based on an input to the fourth pad in response to the second timing signal consisting of i cycles, and the second control information is stored in the third register based on an input to the fourth pad in response to the second timing signal consisting of j cycles.

    MEMORY SYSTEM
    7.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240345734A1

    公开(公告)日：2024-10-17

    申请号：US18631430

    申请日：2024-04-10

    申请人： Kioxia Corporation

    发明人： Kazuhiro HIWADA

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

    摘要： According to one embodiment, a memory system includes a plurality of memory chips each including a first memory area and a second memory area and a memory controller. The memory controller is configured to control a first group including a plurality of first memory areas and a second group including a plurality of second memory areas independently of each other, form a data group including a plurality of write data items of respective pages and first data including an erasure correction code corresponding to the write data items, and distribute each of the write data items and the first data of the data group in the plurality of first memory areas of the first group to write the distributed write data items and first data at different timings.

    Method and system for buffer allocation management for a memory device
    9.
    发明授权
    Method and system for buffer allocation management for a memory device 有权

    公开(公告)号：US12118235B2

    公开(公告)日：2024-10-15

    申请号：US17402192

    申请日：2021-08-13

    申请人： Kioxia Corporation

    发明人： Paul Hanham ,  Julien Margetts ,  Matthew Stephens

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0656 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679

    摘要： Example implementations include a non-transitory processor-readable media comprising processor-readable instructions that when executed by at least one processor of a controller, causes the processor to generate at least one memory address corresponding respectively to at least one command block, the command block being associated with a command to a memory device, allocate the memory address to a buffer addressing unit associated with a host interface, the memory address including a buffer memory identifier associated with a buffer memory block and a buffer memory address associated with the buffer memory block, and update a request count associated with the buffer memory block by incrementing a reference counter associated with the buffer memory block.