公开(公告)号：US12125542B2

公开(公告)日：2024-10-22

申请号：US17695529

申请日：2022-03-15

申请人： KIOXIA CORPORATION

发明人： Wataru Moriyama ,  Hayato Konno ,  Takao Nakajima ,  Fumihiro Kono ,  Masaki Fujiu ,  Kiyoaki Iwasa ,  Tadashi Someya

IPC分类号： G11C16/04 ,  G11C16/16 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

CPC分类号： G11C16/16 ,  G11C16/0483 ,  H01L23/528 ,  H01L23/535 ,  H10B41/27 ,  H10B43/27

摘要： A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.