公开(公告)号：US09105588B2

公开(公告)日：2015-08-11

申请号：US12909458

申请日：2010-10-21

Applicant: Ying-Ju Chen ,  Hsien-Wei Chen

Inventor： Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/3205

CPC classification number: H01L23/3171 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03614 ,  H01L2224/0382 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05562 ,  H01L2224/0558 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2924/01019 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/00

Abstract: A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer.

Abstract translation: 公开了半导体部件上的导电特征。 在衬底上形成第一钝化层。 在第一钝化层上形成接合焊盘。 第二钝化层覆盖第一钝化层和接合焊盘。 第二钝化层具有覆盖接合焊盘的第一开口和暴露第一钝化层的顶表面的多个第二开口。 缓冲层覆盖在第二钝化层上并填充多个第二开口。 缓冲层具有与第一开口重叠的第三开口并且一起暴露接合焊盘的一部分。 组合的第一开口和第三开口具有侧壁。 凸块下金属（UBM）层覆盖在组合的第一开口和第三开口的侧壁上，并且与接合焊盘的暴露部分接触。 导电特征覆盖在UBM层上。

公开(公告)号：US08952530B2

公开(公告)日：2015-02-10

申请号：US13618382

申请日：2012-09-14

Applicant: Hsien-Wei Chen ,  Ying-Ju Chen

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/498

CPC classification number: H01L24/14 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02351 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05569 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1412 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/14 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: A device includes a metal pad, a passivation layer overlapping edge portions of the metal pad, and a first polymer layer over the passivation layer. A Post-Passivation-Interconnect (PPI) has a level portion overlying the first polymer layer, and a plug portion that has a top connected to the level portion. The plug portion extends into the first polymer layer. A bottom surface of the plug portion is in contact with a dielectric material. A second polymer layer is overlying the first polymer layer.

Abstract translation: 一种器件包括金属焊盘，与金属焊盘的边缘部分重叠的钝化层以及钝化层上的第一聚合物层。 后钝化互连（PPI）具有覆盖第一聚合物层的水平部分和具有连接到水平部分的顶部的插头部分。 插头部分延伸到第一聚合物层中。 插头部分的底表面与电介质材料接触。 第二聚合物层覆盖第一聚合物层。

公开(公告)号：US08618827B2

公开(公告)日：2013-12-31

申请号：US12903984

申请日：2010-10-13

Applicant: Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

Inventor： Tung-Liang Shao ,  Shih-Wei Liang ,  Ying-Ju Chen ,  Ching-Jung Yang ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G01R31/2648 ,  G01R31/002 ,  G01R31/2644 ,  G01R31/2884 ,  H01L22/34 ,  H01L2224/13

Abstract: Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer.

Abstract translation: 提供了一种用于测试未封装的半导体晶片的测试结构。 测试结构包括耦合到半导体晶片的互连结构的施力部件。 力施加部件可操作以向半导体晶片施加力。 测试结构还包括耦合到互连结构的第一和第二测试部分。 第一和第二测试部分可操作以测量与互连结构的预定区域相关联的电性能。 第一和第二测试部分可操作以在力施加到半导体晶片时测量电气性能。

公开(公告)号：US20130140706A1

公开(公告)日：2013-06-06

申请号：US13312538

申请日：2011-12-06

Applicant: Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

Inventor： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012

Abstract: A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

Abstract translation: 晶片级芯片级半导体器件包括半导体管芯，第一下凸块金属结构和第二凸块下金属结构。 具有第一外壳的第一下凸块金属结构形成在半导体管芯的拐角区域或边缘区域上。 具有第二外壳的第二下凸块金属结构形成在半导体管芯的内部区域上。 第一个外壳大于第二个外壳。

公开(公告)号：US08278737B2

公开(公告)日：2012-10-02

申请号：US12417394

申请日：2009-04-02

Applicant: Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Shin-Puu Jeng

Inventor： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Shin-Puu Jeng

IPC: H01L21/00

CPC classification number: H01L21/78 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6.

Abstract translation: 提供了一种半导体器件，其包括半导体衬底，形成在半导体衬底上的多个管芯，所述多个管芯沿着第一方向延伸的第一区域彼此分离，并且沿着不同于第二方向的第二方向延伸的第二区域 第一方向，形成在第三区域内的虚设金属结构，所述第三区域包括由所述第一区域和所述第二区域的交点限定的区域，形成在所述基板上的多个金属互连层，以及形成在所述第二区域上的多个电介质层 基质。 每个金属互连层设置在每个介电层内，并且至少一个电介质层的介电常数小于约2.6。

公开(公告)号：US20100117080A1

公开(公告)日：2010-05-13

申请号：US12267021

申请日：2008-11-07

Applicant: Hsien-Wei Chen ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Shin-Puu Jeng

Inventor： Hsien-Wei Chen ,  Ying-Ju Chen ,  Yu-Wen Liu ,  Hao-Yi Tsai ,  Shin-Puu Jeng

IPC: H01L23/485

CPC classification number: H01L22/34 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.

Abstract translation: 具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。 互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。 在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。 在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。 在其他实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

公开(公告)号：US20090283911A1

公开(公告)日：2009-11-19

申请号：US12121541

申请日：2008-05-15

Applicant: Hao-Yi Tsai ,  Yu-Wen Liu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shin-Puu Jeng

Inventor： Hao-Yi Tsai ,  Yu-Wen Liu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shin-Puu Jeng

IPC: H01L23/522

CPC classification number: H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05556 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a second dielectric layer having a second k value greater than the first k value; and second metal lines in the second dielectric layer. The third metallization layer is over the second metallization layer, and includes a third dielectric layer having a third k value; and third metal lines in the third dielectric layer. The integrated circuit structure further includes a bottom passivation layer over the third metallization layer.

Abstract translation: 集成电路结构包括第一，第二和第三金属化层。 第一金属化层包括具有第一k值的第一介电层; 和第一介电层中的第一金属线。 第二金属化层在第一金属化层之上，并且包括具有大于第一k值的第二k值的第二介电层; 和第二介电层中的第二金属线。 第三金属化层在第二金属化层之上，并且包括具有第三k值的第三介电层; 和第三介电层中的第三金属线。 集成电路结构还包括在第三金属化层上的底部钝化层。

公开(公告)号：US08610267B2

公开(公告)日：2013-12-17

申请号：US12840900

申请日：2010-07-21

Applicant: Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

Inventor： Ching-Jung Yang ,  Chang-Pin Huang ,  Tzuan-Horng Liu ,  Michael Shou-Ming Tong ,  Ying-Ju Chen ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC: H01L23/48

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/93 ,  H01L25/0657 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81464 ,  H01L2224/93 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM.

公开(公告)号：US08405211B2

公开(公告)日：2013-03-26

申请号：US12726449

申请日：2010-03-18

Applicant: Hao-Yi Tsai ,  Hsien-Wei Chen ,  Yu-Wen Liu ,  Ying-Ju Chen ,  Hsiu-Ping Wei

Inventor： Hao-Yi Tsai ,  Hsien-Wei Chen ,  Yu-Wen Liu ,  Ying-Ju Chen ,  Hsiu-Ping Wei

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L21/768 ,  H01L21/76877 ,  H01L23/48 ,  H01L23/481 ,  H01L24/03 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/0509 ,  H01L2224/05092 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.

公开(公告)号：US20110284843A1

公开(公告)日：2011-11-24

申请号：US13198408

申请日：2011-08-04

Applicant: Hsien-Wei Chen ,  Chung-Ying Yang ,  Ying-Ju Chen ,  Shih-Wei Liang ,  Ching-Jung Yang

Inventor： Hsien-Wei Chen ,  Chung-Ying Yang ,  Ying-Ju Chen ,  Shih-Wei Liang ,  Ching-Jung Yang

IPC: H01L23/528

CPC classification number: H01L27/0203 ,  H01L22/34 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05553 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure.

Abstract translation: 半导体芯片包括角部应力消除（CSR）区域。 增强的结构将密封环结构的侧面连接到包围CSR区域。 被测设备（DUT）结构设置在CSR区域上。 一组探针垫结构设置在CSR区域上。 探针焊盘结构中的两个电连接到DUT结构。