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    VERTICAL 1T1R STRUCTURE FOR EMBEDDED MEMORY
    4.
    发明公开
    VERTICAL 1T1R STRUCTURE FOR EMBEDDED MEMORY 审中-公开

    公开(公告)号：US20230309325A1

    公开(公告)日：2023-09-28

    申请号：US17701144

    申请日：2022-03-22

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Kuo-Pin Chang ,  Yu-Wei Ting ,  Kuo-Ching Huang

    IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

    CPC classification number: H01L27/2481 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/16 ,  H01L23/5283

    Abstract: Some embodiments relate to an embedded memory device with vertically stacked source, drain and gate connections. The semiconductor memory device includes a substrate and a pillar of channel material extending in a first direction. A bit line is disposed over the pillar of channel material and is coupled to the pillar of channel material, and extends in a second direction that is perpendicular to the first direction. Word lines are on opposite sides of the pillar of channel material and extend in a third direction. The third direction is perpendicular to the second direction. A dielectric layer separates the word lines from the pillar of channel material. Source lines extend in the third direction over the substrate, directly beneath the word lines. Variable resistance memory layers are between the source lines and an outer sidewall of the dielectric layer, laterally surrounding the sidewalls of the pillar of channel material.

    Embedded Transistor
    5.
    发明申请
    Embedded Transistor 审中-公开

    公开(公告)号：US20170229467A1

    公开(公告)日：2017-08-10

    申请号：US15495652

    申请日：2017-04-24

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

    IPC: H01L27/108 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/423

    Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.

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