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15 条记录 (耗时 0.021 秒)

    HEAT CONTROLLED SWITCH
    1.
    发明公开
    HEAT CONTROLLED SWITCH 审中-公开

    公开(公告)号：US20230402241A1

    公开(公告)日：2023-12-14

    申请号：US17834944

    申请日：2022-06-08

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Wei Ting ,  Kuo-Pin Chang ,  Hung-Ju Li ,  Kuo-Ching Huang

    IPC分类号： H01H37/12 ,  H01H37/32

    CPC分类号： H01H37/12 ,  H01L35/12 ,  H01H37/32

    摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, and a heater element on the semiconductor substrate, the heater element configured to generate heat in response to a current flowing therethrough. The semiconductor device also includes a conductor material having a programmable conductivity, and an insulator layer between the heater element and the conductor material, where the conductor material is configured to be programmed by applying one or more voltage differences to one or more of the heater element and the conductor material, and where a capacitance between the conductor material and the heater element is configured to be controlled by the voltage differences such that the capacitance is lower while the conductor material is being programmed than while the conductor material is not being programmed.

    VERTICAL 1T1R STRUCTURE FOR EMBEDDED MEMORY
    5.
    发明公开
    VERTICAL 1T1R STRUCTURE FOR EMBEDDED MEMORY 审中-公开

    公开(公告)号：US20230309325A1

    公开(公告)日：2023-09-28

    申请号：US17701144

    申请日：2022-03-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kuo-Pin Chang ,  Yu-Wei Ting ,  Kuo-Ching Huang

    IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L23/528

    CPC分类号： H01L27/2481 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/16 ,  H01L23/5283

    摘要： Some embodiments relate to an embedded memory device with vertically stacked source, drain and gate connections. The semiconductor memory device includes a substrate and a pillar of channel material extending in a first direction. A bit line is disposed over the pillar of channel material and is coupled to the pillar of channel material, and extends in a second direction that is perpendicular to the first direction. Word lines are on opposite sides of the pillar of channel material and extend in a third direction. The third direction is perpendicular to the second direction. A dielectric layer separates the word lines from the pillar of channel material. Source lines extend in the third direction over the substrate, directly beneath the word lines. Variable resistance memory layers are between the source lines and an outer sidewall of the dielectric layer, laterally surrounding the sidewalls of the pillar of channel material.

    MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    7.
    发明公开
    MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开

    公开(公告)号：US20230209836A1

    公开(公告)日：2023-06-29

    申请号：US17725013

    申请日：2022-04-20

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kuo-Pin Chang ,  Chien Hung Liu

    IPC分类号： H01L27/1159 ,  H01L27/11597

    CPC分类号： H01L27/1159 ,  H01L27/11597

    摘要： A memory device having a 3D structure provides MFMIS-FET memory cells with a high chip area density. The memory device includes a stack of memory cell layers interleaved with insulating layers. Channel vias penetrate through the stack. Channels of the memory cells are disposed in the channel vias. MFM portions of memory cells are sandwiched between the insulating layers in areas lateral to the channel vias. The MFM portions may be radially distributed from the channel vias and include a floating gate, a ferroelectric layer, and a gate electrode. The gate electrodes associated with a plurality of MFM structures may be united into a word line gate. The ferroelectric layer may wrap around the word line gate, whereby the ferroelectric layer is disposed above and below the word line gate as well as between the word line gate and each of the floating gates.

    CROSS-POINT ARCHITECTURE FOR PCRAM
    9.
    发明公开
    CROSS-POINT ARCHITECTURE FOR PCRAM 审中-公开

    公开(公告)号：US20230380194A1

    公开(公告)日：2023-11-23

    申请号：US17751638

    申请日：2022-05-23

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kuo-Pin Chang ,  Kuo-Ching Huang

    IPC分类号： H01L27/24 ,  H01L45/00 ,  G11C5/06

    CPC分类号： H01L27/249 ,  H01L27/2436 ,  H01L45/06 ,  G11C5/063 ,  H01L45/1608

    摘要： A cell array of a memory device includes: a first deck of memory cells arranged in a first row and a second row extending in a first horizontal direction and a plurality of columns extending in a second horizontal direction, wherein the memory cells in the second row in the first deck is displaced in the first horizontal direction with respect to the memory cells in the first row in the first deck; a first common word line metal track extending in the first horizontal direction, wherein both the memory cells in the first row and the memory cells in the second row are disposed on the first common word line metal track; and a plurality of first bit line metal tracks extending in the second horizontal direction, wherein each of the plurality of first bit line metal tracks is disposed on one of the first deck of memory cells.