公开(公告)号：US12063785B2

公开(公告)日：2024-08-13

申请号：US17462663

申请日：2021-08-31

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Kuo-Pin Chang ,  Chien Hung Liu ,  Chih-Wei Hung

IPC分类号： H10B51/20 ,  H10B51/30

CPC分类号： H10B51/20 ,  H10B51/30

摘要： A memory cell, an integrated circuit and method of manufacturing the same are provided. The memory device includes a substrate, gate layers and insulating layers, an isolation column, a channel layer, a first conductive feature, a second conductive feature, a storage layer and a pair of isolation structures. The isolation column extends through the gate layers and the insulating layers along a first direction. The channel layer laterally covers the isolation column. The first conductive feature and second conductive feature extend along the first direction and adjacent to the isolation column. The storage layer is disposed between the gate layers and the channel layer. The pair of isolation structures extends along the first direction. The pair of isolation structures includes a first isolation structure disposed between the first conductive feature and the gate layers, and a second isolation structure disposed between the second conductive feature and the gate layers.

公开(公告)号：US11678491B2

公开(公告)日：2023-06-13

申请号：US17336780

申请日：2021-06-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien Hung Liu ,  Chih-Wei Hung

IPC分类号： H10B43/30 ,  H01L27/11568 ,  G11C16/24 ,  H01L27/11573 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/84 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/265 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  G11C16/08 ,  G11C16/22 ,  H01L29/792 ,  H01L27/12 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  G11C16/04

CPC分类号： H01L27/11568 ,  G11C16/08 ,  G11C16/22 ,  G11C16/24 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/40117 ,  H01L29/42328 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792 ,  G11C16/0466 ,  H01L29/665

摘要： An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high κ dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.

公开(公告)号：US20230387020A1

公开(公告)日：2023-11-30

申请号：US17825345

申请日：2022-05-26

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien Hung Liu ,  Kuo-Ching Huang ,  Harry-Hak-Lay Chuang ,  Wei-Cheng Wu

IPC分类号： H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L23/53295 ,  H01L24/08 ,  H01L24/80 ,  H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76832 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

摘要： The present disclosure relates to an integrated chip including a first dielectric layer overlying a substrate and a first conductive interconnect within the first dielectric layer. A bonding layer is over the first dielectric layer. The bonding layer includes a bonding dielectric layer and a bonding interconnect in the bonding dielectric layer. A first charged dielectric layer is along a bottom of the first dielectric layer. A second charged dielectric layer is along a top of the first dielectric layer. The first charged dielectric layer and the second charged dielectric layer have a same polarity.

公开(公告)号：US20210288059A1

公开(公告)日：2021-09-16

申请号：US17336780

申请日：2021-06-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chien Hung Liu ,  Chih-Wei Hung

IPC分类号： H01L27/11568 ,  G11C16/24 ,  H01L27/11573 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L21/84 ,  H01L21/3213 ,  H01L21/321 ,  H01L21/265 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  G11C16/08 ,  G11C16/22 ,  H01L29/792 ,  H01L27/12 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51

摘要： An integrated circuit (IC) includes a semiconductor-on-insulator (SOI) substrate comprising a handle substrate, an insulator layer over the handle substrate, and a semiconductor device layer over the insulator layer. A logic device includes a logic gate arranged over the semiconductor device layer. The logic gate is arranged within a high κ dielectric layer. A memory cell includes a control gate and a select gate laterally adjacent to one another and arranged over the semiconductor device layer. A charge-trapping layer underlies the control gate.

公开(公告)号：US11574917B2

公开(公告)日：2023-02-07

申请号：US17099647

申请日：2020-11-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chien Hung Liu

IPC分类号： H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11575

摘要： A method of forming a memory device is provided. The method comprises: forming a first storage portion on a substrate; forming a conductive layer on the first storage portion, wherein the conductive layer has a first surface coupled to the first storage portion; and forming a second storage portion on a second surface of the conductive layer, wherein the second surface is opposite to the first surface.

公开(公告)号：US20230209836A1

公开(公告)日：2023-06-29

申请号：US17725013

申请日：2022-04-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo-Pin Chang ,  Chien Hung Liu

IPC分类号： H01L27/1159 ,  H01L27/11597

CPC分类号： H01L27/1159 ,  H01L27/11597

摘要： A memory device having a 3D structure provides MFMIS-FET memory cells with a high chip area density. The memory device includes a stack of memory cell layers interleaved with insulating layers. Channel vias penetrate through the stack. Channels of the memory cells are disposed in the channel vias. MFM portions of memory cells are sandwiched between the insulating layers in areas lateral to the channel vias. The MFM portions may be radially distributed from the channel vias and include a floating gate, a ferroelectric layer, and a gate electrode. The gate electrodes associated with a plurality of MFM structures may be united into a word line gate. The ferroelectric layer may wrap around the word line gate, whereby the ferroelectric layer is disposed above and below the word line gate as well as between the word line gate and each of the floating gates.

公开(公告)号：US20220415929A1

公开(公告)日：2022-12-29

申请号：US17397160

申请日：2021-08-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Hsin Fu Lin ,  Chien Hung Liu

IPC分类号： H01L27/12 ,  H01L21/762 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

摘要： Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. The substrate includes a metal layer, a device layer disposed over the metal layer, and an insulating layer disposed vertically between the metal layer and the device layer. A semiconductor device is disposed on the device layer. An interlayer dielectric (ILD) layer is disposed over the semiconductor device and the substrate.

公开(公告)号：US10854618B2

公开(公告)日：2020-12-01

申请号：US15719466

申请日：2017-09-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chien Hung Liu

IPC分类号： H01L27/11524 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11575

摘要： A memory device includes: a conductive layer coupled to a reference voltage level; a first storage portion vertically coupled to a first surface of the conductive layer; and a second storage portion vertically coupled to a second surface of the conductive layer; wherein the second surface is opposite to the first surface.

公开(公告)号：US20240088026A1

公开(公告)日：2024-03-14

申请号：US18155569

申请日：2023-01-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yi Ching Ong ,  Wei-Cheng Wu ,  Chien Hung Liu ,  Harry-Haklay Chuang ,  Yu-Sheng Chen ,  Yu-Jen Wang ,  Kuo-Ching Huang

IPC分类号： H01L23/522 ,  H01F17/00 ,  H01L23/48 ,  H01L23/498

CPC分类号： H01L23/5227 ,  H01F17/0013 ,  H01L23/481 ,  H01L23/49822 ,  H01L28/10 ,  H01F2017/0073

摘要： A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.

公开(公告)号：US11837643B2

公开(公告)日：2023-12-05

申请号：US17200865

申请日：2021-03-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chien Hung Liu

IPC分类号： H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H01L29/06 ,  H01L21/28 ,  H01L29/417 ,  H01L29/78 ,  H10B41/30

CPC分类号： H01L29/42324 ,  H01L29/0649 ,  H01L29/40114 ,  H01L29/41783 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/7881 ,  H10B41/30

摘要： A semiconductor device includes a substrate, a gate structure disposed over the substrate, a drain structure disposed in the substrate, and a source structure disposed in the substrate on an n opposite side of the gate structure from the drain structure. The substrate includes a first semiconductor layer, a second semiconductor layer over the first semiconductor layer, and an insulating layer sandwiched between the first semiconductor layer and the second semiconductor layer. The source structure and the drain structure include a same conductivity type. The source structure includes at least an epitaxial layer. The source structure extends deeper into the substrate than the drain structure.