公开(公告)号：US20160268430A1

公开(公告)日：2016-09-15

申请号：US15161994

申请日：2016-05-23

申请人： Soitec

发明人： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC分类号： H01L29/78 ,  H01L21/84 ,  H01L29/165 ,  H01L27/12 ,  H01L29/08 ,  H01L29/161 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

摘要： Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

摘要翻译： 形成半导体结构的方法包括提供具有覆盖在掩埋氧化物层上方的应变初级半导体层的外延基底层的多层衬底。 外延基底层内的元素用于改变多层基底的第一区域内的初级半导体层中的应变状态，而不改变多层基底的第二区域内的初级半导体层中的应变状态。 形成第一多个晶体管沟道结构，每个晶体管沟道结构各自包括多层衬底的第一区域内的初级半导体层的一部分，并且形成第二多个晶体管沟道结构，每个晶体管沟道结构各自包括初级半导体层的一部分 在多层基板的第二区域内。 通过这种方法制造的半导体结构可以包括具有不同应变状态的晶体管沟道结构。

公开(公告)号：US20160087100A1

公开(公告)日：2016-03-24

申请号：US14938545

申请日：2015-11-11

申请人： Soitec

发明人： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/165 ,  H01L27/12

CPC分类号： H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

摘要： Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

公开(公告)号：US20230170264A1

公开(公告)日：2023-06-01

申请号：US17995791

申请日：2021-03-29

申请人： Soitec

发明人： Trong Hyunh-Bao ,  Bich-Yen Nguyen ,  Christophe Maleville

IPC分类号： H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L21/762

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/42376 ,  H01L21/76281

摘要： A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: —a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, —a source region and a drain region, and —a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.

公开(公告)号：US20170084478A1

公开(公告)日：2017-03-23

申请号：US15264821

申请日：2016-09-14

申请人： Soitec ,  Peregrine Semiconductor Corporation

发明人： Bich-Yen Nguyen ,  Christophe Maleville ,  Sinan Goktepeli ,  Anthony Mark Miscione ,  Alain Duvallet

IPC分类号： H01L21/763 ,  H01L23/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/04 ,  H01L29/16

CPC分类号： H01L21/763 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L23/66 ,  H01L27/13 ,  H01L29/04 ,  H01L29/16

摘要： The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from the interface of the polycrystalline silicon layer with the monocrystalline layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the portion.

公开(公告)号：US20240170284A1

公开(公告)日：2024-05-23

申请号：US18550044

申请日：2022-03-03

申请人： Soitec

发明人： Gweltaz Gaudin ,  Christophe Maleville ,  lonut Radu ,  Hugo Biard

IPC分类号： H01L21/02 ,  C23C16/02 ,  C23C16/32 ,  C23C16/56 ,  H01L21/762

CPC分类号： H01L21/02529 ,  C23C16/0227 ,  C23C16/325 ,  C23C16/56 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/76254

摘要： A method for producing a semiconductor structure, comprises: a) providing a temporary substrate made of graphite having a grain size of between 4 microns and 35 microns, a porosity of between 6 and 17%, and a coefficient of thermal expansion of between 4×10-6/° C. and 5×10-6/° C.; b) depositing, on a front face of the temporary substrate, a carrier layer made of polycrystalline silicon carbide having a thickness of between 10 microns and 200 microns, c) transferring a working layer made of monocrystalline silicon carbide to the carrier layer to form a composite structure, the transfer implementing bonding by molecular adhesion, d) forming an active layer on the working layer, e) and removing the temporary substrate to form the semiconductor structure, the structure including the active layer, the working layer and the carrier layer. A composite structure is obtained in an intermediate step of the production method.

公开(公告)号：US20230260841A1

公开(公告)日：2023-08-17

申请号：US17756615

申请日：2020-10-26

申请人： Soitec

发明人： Ionut Radu ,  Hugo Biard ,  Christophe Maleville ,  Eric Guiot ,  Didier Landru

IPC分类号： H01L21/78 ,  H01L21/02 ,  C30B29/36 ,  C30B25/20 ,  C30B31/22 ,  C30B33/10 ,  C23C16/32

CPC分类号： H01L21/7813 ,  H01L21/02079 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02628 ,  C30B29/36 ,  C30B25/20 ,  C30B31/22 ,  C30B33/10 ,  C23C16/325

摘要： A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.

公开(公告)号：US09576798B2

公开(公告)日：2017-02-21

申请号：US14934567

申请日：2015-11-06

申请人： Soitec

发明人： Bich-Yen Nguyen ,  Walter Schwarzenbach ,  Christophe Maleville

IPC分类号： H01L21/8238 ,  H01L27/12 ,  H01L21/266 ,  H01L21/336 ,  H01L21/225 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L21/84 ,  H01L21/762 ,  H01L29/10

CPC分类号： H01L21/2253 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/76251 ,  H01L21/76281 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/32 ,  H01L29/7849

摘要： Methods of fabricating a semiconductor structure include providing a semiconductor-on-insulator (SOI) substrate including a base substrate, a strained stressor layer above the base substrate, a surface semiconductor layer, and a dielectric layer between the stressor layer and the surface semiconductor layer. Ions are implanted into or through a first region of the stressor layer, and additional semiconductor material is formed on the surface semiconductor layer above the first region of the stressor layer. The strain state in the first region of the surface semiconductor layer above the first region of the stressor layer is altered, and a trench structure is formed at least partially into the base substrate. The strain state is altered in a second region of the surface semiconductor layer above the second region of the stressor layer. Semiconductor structures are fabricated using such methods.

摘要翻译： 制造半导体结构的方法包括提供包括基底基板，在基底基板上方的应变应力层，表面半导体层和应力层与表面半导体层之间的电介质层的绝缘体上半导体 。 离子被注入或穿过应力层的第一区域，并且在应力层的第一区域上方的表面半导体层上形成附加的半导体材料。 在应力层的第一区域上方的表面半导体层的第一区域中的应变状态被改变，并且沟槽结构至少部分地形成到基底衬底中。 在应力层的第二区域上方的表面半导体层的第二区域中改变应变状态。 使用这种方法制造半导体结构。

公开(公告)号：US20160372484A1

公开(公告)日：2016-12-22

申请号：US15176925

申请日：2016-06-08

申请人： Soitec

发明人： Bich-Yen Nguyen ,  Frederic Allibert ,  Christophe Maleville

IPC分类号： H01L27/12 ,  H01L21/266 ,  H01L21/84 ,  H01L23/66

CPC分类号： H01L27/1203 ,  H01L21/26506 ,  H01L21/26533 ,  H01L21/266 ,  H01L21/84 ,  H01L23/66

摘要： A method for manufacturing a high-resistivity semiconductor-on-insulator substrate comprising the steps of: a) forming a dielectric layer and a semiconductor layer over a high-resistivity substrate, such that the dielectric layer is arranged between the high-resistivity substrate and the semiconductor layer; b) forming a hard mask or resist over the semiconductor layer, wherein the hard mask or resist has at least one opening at a predetermined position; c) forming at least one doped region in the high-resistivity substrate by ion implantation of an impurity element through the at least one opening of the hard mask or resist, the semiconductor layer and the dielectric layer; d) removing the hard mask or resist; and e) forming a radiofrequency, RF, circuit in and/or on the semiconductor layer at least partially overlapping the at least one doped region in the high-resistivity substrate.

摘要翻译： 一种用于制造绝缘体上绝缘体上的高电阻半导体衬底的方法，包括以下步骤：a）在高电阻率衬底上形成电介质层和半导体层，使得电介质层布置在高电阻率衬底和 半导体层; b）在所述半导体层上形成硬掩模或抗蚀剂，其中所述硬掩模或抗蚀剂在预定位置具有至少一个开口; c）通过所述硬掩模或抗蚀剂，所述半导体层和所述电介质层的所述至少一个开口离子注入杂质元素，在所述高电阻率衬底中形成至少一个掺杂区域; d）去除硬掩模或抗蚀剂; 以及e）在所述半导体层中和/或之上形成至少部分地与所述高电阻率衬底中的所述至少一个掺杂区域重叠的射频RF电路。

公开(公告)号：US09219150B1

公开(公告)日：2015-12-22

申请号：US14489817

申请日：2014-09-18

申请人： Soitec

发明人： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC分类号： H01L23/52 ,  H01L21/8238 ,  H01L21/30 ,  H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L21/306 ,  H01L21/265 ,  H01L21/22 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

摘要： Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

摘要翻译： 形成半导体结构的方法包括提供具有覆盖在掩埋氧化物层上方的应变初级半导体层的外延基底层的多层衬底。 外延基底层内的元素用于改变多层基底的第一区域内的初级半导体层中的应变状态，而不改变多层基底的第二区域内的初级半导体层中的应变状态。 形成第一多个晶体管沟道结构，每个晶体管沟道结构各自包括多层衬底的第一区域内的初级半导体层的一部分，并且形成第二多个晶体管沟道结构，每个晶体管沟道结构各自包括初级半导体层的一部分 在多层基板的第二区域内。 通过这种方法制造的半导体结构可以包括具有不同应变状态的晶体管沟道结构。

公开(公告)号：US12100727B2

公开(公告)日：2024-09-24

申请号：US17418148

申请日：2019-12-23

申请人： Soitec

发明人： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Damien Massy ,  Nadia Ben Mohamed ,  Nicolas Daval ,  Christophe Girard ,  Christophe Maleville

IPC分类号： H01L27/146 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L31/18

CPC分类号： H01L27/14683 ,  H01L21/26506 ,  H01L21/3223 ,  H01L21/3226 ,  H01L21/76254 ,  H01L27/1463 ,  H01L31/1892

摘要： A method of manufacturing a substrate for a front-facing image sensor, comprises:—providing a donor substrate comprising a semiconductor layer to be transferred,—providing a semiconductor carrier substrate,—bonding the donor substrate to the carrier substrate, an electrically insulating layer being at the bonding interface,—transferring the semiconductor layer to the carrier substrate,—implanting gaseous ions in the carrier substrate via the transferred semiconductor layer and the electrically insulating layer, and—after the implantation, epitaxially growing an additional semiconductor layer on the transferred semiconductor layer.