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    Variable resistance memory devices
    1.
    发明授权
    Variable resistance memory devices 有权

    公开(公告)号：US11514954B2

    公开(公告)日：2022-11-29

    申请号：US17335520

    申请日：2021-06-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Boram Im ,  Hongsoo Kim ,  Jongkook Park ,  Hose Choi ,  Hyunju Sung

    IPC: G11C5/06 ,  G11C13/00

    Abstract: An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.

    Three-dimensional semiconductor memory device
    4.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US10032787B2

    公开(公告)日：2018-07-24

    申请号：US15652411

    申请日：2017-07-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yoocheol Shin ,  Hongsoo Kim ,  Jaesung Sim

    IPC: H01L27/115 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11548 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11531 ,  H01L27/105

    Abstract: A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10546869B2

    公开(公告)日：2020-01-28

    申请号：US15800545

    申请日：2017-11-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taekeun Cho ,  Hongsoo Kim ,  Jong-Kook Park ,  TaeHee Lee

    IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11524 ,  H01L23/522 ,  H01L27/11578 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

    Abstract: A semiconductor device comprises a plurality of stack structures that include gate electrodes sequentially stacked on a substrate and are disposed along a first direction, and a plurality of separating insulation layers each of which is disposed between the stack structures. A plurality of vertical pillars penetrate each of the stack structures and are connected to the substrate. A plurality of bit lines are disposed on the vertical pillars and run across the stack structures in the first direction. A plurality of bit line contact structures connect the vertical pillars to the bit lines. A plurality of first cell dummy lines are disposed on the plurality of separating insulation layers and extend in a second direction crossing the first direction.

    Semiconductor device
    10.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09559116B2

    公开(公告)日：2017-01-31

    申请号：US14695051

    申请日：2015-04-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hongsoo Kim ,  HunKook Lee ,  Jeehoon Hwang

    IPC: H01L27/115

    CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

    Abstract: A semiconductor device may include an insulating layer provided in one body on a substrate, a first gate electrode and a second gate electrode disposed on the insulating layer, the first and second gate electrodes extending in a first direction parallel to a top surface of the substrate, a first channel structure penetrating the first gate electrode and the insulating layer so as to be connected to the substrate, a second channel structure penetrating the second gate electrode and the insulating layer so as to be connected to the substrate, and a contact penetrating the insulating layer between the first gate electrode and the second gate electrode. The contact may be connected to a common source region formed in the substrate, and the common source region may have a first conductivity type. Further, the first gate electrode and the second gate electrode may be spaced apart from each other in a second direction at the same level from the substrate, wherein the second direction intersects the first direction and is parallel to the top surface of the substrate.

    Abstract translation: 半导体器件可以包括设置在基板上的一个主体中的绝缘层，设置在绝缘层上的第一栅电极和第二栅电极，第一和第二栅电极沿平行于基板顶表面的第一方向延伸 贯穿第一栅极电极和绝缘层以连接到基板的第一通道结构，穿过第二栅极电极和绝缘层的第二通道结构以连接到基板，以及穿过第二通道结构 第一栅极电极和第二栅极电极之间的绝缘层。 接触可以连接到形成在基板中的公共源极区域，并且公共源极区域可以具有第一导电类型。 此外，第一栅极电极和第二栅极电极可以在与基板相同的第二方向上彼此间隔开，其中第二方向与第一方向相交并且平行于基板的顶表面。

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