公开(公告)号：US11514954B2

公开(公告)日：2022-11-29

申请号：US17335520

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boram Im ,  Hongsoo Kim ,  Jongkook Park ,  Hose Choi ,  Hyunju Sung

IPC: G11C5/06 ,  G11C13/00

Abstract: An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.

公开(公告)号：US20220130430A1

公开(公告)日：2022-04-28

申请号：US17335520

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boram Im ,  Hongsoo Kim ,  Jongkook Park ,  Hose Choi ,  Hyunju Sung

IPC: G11C5/06 ,  G11C13/00

Abstract: An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.