公开(公告)号：US10388604B2

公开(公告)日：2019-08-20

申请号：US15956006

申请日：2018-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseop Yoon ,  Hyung Jong Lee ,  Boram Im

IPC: H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L29/78 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L27/092 ,  H01L29/165 ,  H01L21/8238

Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.

公开(公告)号：US20180233450A1

公开(公告)日：2018-08-16

申请号：US15956006

申请日：2018-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseop Yoon ,  Hyung Jong Lee ,  Boram Im

IPC: H01L23/528 ,  H01L29/78 ,  H01L27/02 ,  H01L23/532 ,  H01L21/8238 ,  H01L23/535 ,  H01L29/165

CPC classification number: H01L23/5283 ,  H01L21/76895 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.

公开(公告)号：US20220130430A1

公开(公告)日：2022-04-28

申请号：US17335520

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boram Im ,  Hongsoo Kim ,  Jongkook Park ,  Hose Choi ,  Hyunju Sung

IPC: G11C5/06 ,  G11C13/00

Abstract: An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.

公开(公告)号：US11514954B2

公开(公告)日：2022-11-29

申请号：US17335520

申请日：2021-06-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boram Im ,  Hongsoo Kim ,  Jongkook Park ,  Hose Choi ,  Hyunju Sung

IPC: G11C5/06 ,  G11C13/00

Abstract: An integrated circuit memory device includes a plurality of row selection transistors and a dummy row selection transistor, on a substrate. A plurality of word lines and a plurality of dummy word lines are also provided on the substrate. A plurality of memory cells are provided, which are electrically connected to corresponding ones of the plurality of word lines. A plurality of dummy memory cells are provided, which are electrically connected to corresponding ones of the plurality of dummy word lines. A first wiring structure is provided, which electrically connects a first one of the plurality of word lines to a first one of the plurality of row selection transistors, and a second wiring structure is provided, which electrically connects the plurality of dummy word lines together and to the dummy row selection transistor.

公开(公告)号：US09978684B2

公开(公告)日：2018-05-22

申请号：US15082820

申请日：2016-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseop Yoon ,  Hyung Jong Lee ,  Boram Im

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/535 ,  H01L23/532 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/02 ,  H01L29/165

CPC classification number: H01L23/5283 ,  H01L21/823871 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/7851

Abstract: The inventive concepts relate to a semiconductor device including a field effect transistor and a method for manufacturing the same. The semiconductor device includes a substrate including first and second source/drain regions formed thereon, a gate electrode intersecting the substrate between the first and second source/drain regions, and an active contact electrically connecting the first and second source/drain regions to each other. The active contact is spaced apart from the gate electrode. The active contact includes first sub-contacts provided on the first and second source/drain regions so as to be connected to the first and second source/drain regions, respectively, a second sub-contact provided on the first sub-contacts to electrically connect the first sub-contacts to each other, and a barrier layer provided between the second sub-contact and each of the first sub-contacts.