公开(公告)号：US09559116B2

公开(公告)日：2017-01-31

申请号：US14695051

申请日：2015-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hongsoo Kim ,  HunKook Lee ,  Jeehoon Hwang

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device may include an insulating layer provided in one body on a substrate, a first gate electrode and a second gate electrode disposed on the insulating layer, the first and second gate electrodes extending in a first direction parallel to a top surface of the substrate, a first channel structure penetrating the first gate electrode and the insulating layer so as to be connected to the substrate, a second channel structure penetrating the second gate electrode and the insulating layer so as to be connected to the substrate, and a contact penetrating the insulating layer between the first gate electrode and the second gate electrode. The contact may be connected to a common source region formed in the substrate, and the common source region may have a first conductivity type. Further, the first gate electrode and the second gate electrode may be spaced apart from each other in a second direction at the same level from the substrate, wherein the second direction intersects the first direction and is parallel to the top surface of the substrate.

Abstract translation: 半导体器件可以包括设置在基板上的一个主体中的绝缘层，设置在绝缘层上的第一栅电极和第二栅电极，第一和第二栅电极沿平行于基板顶表面的第一方向延伸 贯穿第一栅极电极和绝缘层以连接到基板的第一通道结构，穿过第二栅极电极和绝缘层的第二通道结构以连接到基板，以及穿过第二通道结构 第一栅极电极和第二栅极电极之间的绝缘层。 接触可以连接到形成在基板中的公共源极区域，并且公共源极区域可以具有第一导电类型。 此外，第一栅极电极和第二栅极电极可以在与基板相同的第二方向上彼此间隔开，其中第二方向与第一方向相交并且平行于基板的顶表面。

公开(公告)号：US09390214B2

公开(公告)日：2016-07-12

申请号：US14576695

申请日：2014-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： HunKook Lee ,  Hongsoo Kim ,  Juyeon Lee

IPC: H01L21/70 ,  G06F17/50 ,  G03F1/00 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/02

CPC classification number: G06F17/5072 ,  G03F1/00 ,  G06F17/5081 ,  H01L21/823437 ,  H01L21/823456 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0653

Abstract: Methods of preparing layouts for semiconductor devices and semiconductor devices fabricated using the layouts are provided. Preparing the layouts for semiconductor devices may include disposing assistant patterns near a main gate pattern that is provided on a weak active pattern. The weak active pattern may be, for example, an outermost one of active patterns and may be one expected to have an increased width during a fabrication process.

Abstract translation: 提供了使用布局制造的半导体器件和半导体器件布局的方法。 准备半导体器件的布局可以包括将辅助图案布置在提供在弱有源图案上的主栅格图案附近。 弱活性图案可以是例如活性图案中最外面的一种，并且可以是预期在制造过程中具有增加的宽度的活性图案。