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公开(公告)号:US20230093892A1
公开(公告)日:2023-03-30
申请号:US17685942
申请日:2022-03-03
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yumin KIM , Doyoon KIM , Seyun KIM , Hyunjae SONG , Seungyeul YANG
Abstract: Disclosed are a memory device including a vertical stack structure, a method of manufacturing the same, and/or an electronic device including the memory device. The memory device including a vertical stack structure includes an oxygen scavenger layer on a base substrate, a recording material layer on the oxygen scavenger layer and in direct contact with the oxygen scavenger layer, a channel layer on the recording material layer, a gate insulating layer on the channel layer, and a gate electrode on the gate insulating layer. The oxygen scavenger layer includes an element that forms oxygen vacancies in the recording material layer and does not include oxygen.
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公开(公告)号:US20220316052A1
公开(公告)日:2022-10-06
申请号:US17711147
申请日:2022-04-01
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sangwon KIM , Kyung-Eun BYUN , Yeonchoo CHO , Keunwook SHIN , Eunkyu LEE , Changseok LEE , Hyunjae SONG , Hyeonjin SHIN , Jungsoo YOON , Soyoung LEE , Hyunseok LIM
IPC: C23C16/26 , H01L29/45 , H01L21/285 , C23C16/511 , C23C16/505 , C23C16/02
Abstract: Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μm2 or higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.
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公开(公告)号:US20220173221A1
公开(公告)日:2022-06-02
申请号:US17398363
申请日:2021-08-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyeonjin SHIN , Sangwon KIM , Kyung-Eun BYUN , Hyunjae SONG , Keunwook SHIN , Eunkyu LEE , Changseok LEE , Yeonchoo CHO , Taejin CHOI
IPC: H01L29/45 , H01L27/108 , H01L29/15 , H01L29/40
Abstract: An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of a peripheral region of the semiconductor layer, a metal layer facing the semiconductor layer, a graphene layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the graphene layer and the semiconductor and covering the first region.
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公开(公告)号:US20210372786A1
公开(公告)日:2021-12-02
申请号:US17145966
申请日:2021-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Eunkyu LEE , Yeonchoo CHO , Sangwon KIM , Kyung-Eun BYUN , Hyunjae SONG , Hyeonjin SHIN
IPC: G01B15/02 , H01L21/66 , H01L21/285 , H01L29/45 , G01N23/2208
Abstract: A method of calculating a thickness of a graphene layer and a method of measuring a content of silicon carbide, by using X-ray photoelectron spectroscopy (XPS), are provided. The method of calculating the thickness of the graphene layer, which is directly grown on a silicon substrate, includes measuring the thickness of the graphene layer directly grown on the silicon substrate, by using a ratio between a signal intensity of a photoelectron beam emitted from the graphene layer and a signal intensity of a photoelectron beam emitted from the silicon substrate.
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公开(公告)号:US20210313169A1
公开(公告)日:2021-10-07
申请号:US17208216
申请日:2021-03-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyunjae SONG , Kaoru YAMAMOTO , Changhyun KIM , Shuji MORIYA , Jungsoo YOON , Soyoung LEE , Changseok LEE
IPC: H01L21/02 , H01L21/428 , H01L21/3213 , H01J37/32
Abstract: Provided are apparatuses for manufacturing semiconductor devices. An apparatus includes a reaction chamber having a stage to be loaded on a substrate, wherein set plasma is formed over the stage, a plurality of gas supply lines connected to the reaction chamber, flow controllers formed on the plurality of gas supply lines, respectively, to control the amount of a gas supplied to the reaction chamber, and a gas splitter configured to supply a mixed gas to the flow controllers. The apparatus may be a thin film deposition apparatus using plasma and further include a flow control unit connected to the gas splitter and a gas supply source connected to the flow control unit.
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6.
公开(公告)号:US20200266153A1
公开(公告)日:2020-08-20
申请号:US16866033
申请日:2020-05-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyunjae SONG , Seunggeol NAM , Yeonchoo CHO , Seongjun PARK , Hyeonjin SHIN , Jaeho LEE
IPC: H01L23/532 , H01L21/768 , H01L23/522
Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.
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7.
公开(公告)号:US20190157212A1
公开(公告)日:2019-05-23
申请号:US16257189
申请日:2019-01-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyunjae SONG , Seunggeol NAM , Yeonchoo CHO , Seongjun PARK , Hyeonjin SHIN , Jaeho LEE
IPC: H01L23/532 , H01L21/768 , H01L23/522
CPC classification number: H01L23/53209 , H01L21/76843 , H01L21/76846 , H01L21/76849 , H01L21/76852 , H01L23/5226
Abstract: Example embodiments relate to a layer structure having a diffusion barrier layer, and a method of manufacturing the same. The layer structure includes first and second material layers and a diffusion barrier layer therebetween. The diffusion barrier layer includes a nanocrystalline graphene (nc-G) layer. In the layer structure, the diffusion barrier layer may further include a non-graphene metal compound layer or a graphene layer together with the nc-G layer. One of the first and second material layers is an insulating layer, a metal layer, or a semiconductor layer, and the remaining layer may be a metal layer.
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公开(公告)号:US20180190800A1
公开(公告)日:2018-07-05
申请号:US15904967
申请日:2018-02-26
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyungeun BYUN , Jisoo KYOUNG , Seongjun PARK , Hyeonjin SHIN , Hyunjae SONG , Jaeho LEE
CPC classification number: H01L29/66977 , H01L29/456 , H01L29/78
Abstract: An electronic device includes a semiconductor layer, a tunneling layer formed of a material including a two-dimensional (2D) material so as to directly contact a certain region of the semiconductor layer, and a metal layer formed on the tunneling layer.
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公开(公告)号:US20250029656A1
公开(公告)日:2025-01-23
申请号:US18774249
申请日:2024-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Yumin KIM , Seyun KIM , Garam PARK , Hyunjae SONG , Seungyeul YANG , Seungdam HYUN
IPC: G11C13/00
Abstract: A memory device including a variable serial resistive element having a voltage dividing effect and an operating method thereof are disclosed. The memory device includes a memory unit, a variable serial resistive element connected to the memory unit, a controller connected to the variable serial resistive element and configured to control a resistance of the variable serial resistive element, and a power source connected to the variable serial resistive element. The operating method of the memory device includes maintaining a resistance of a serial resistive element connected to a memory element as a first resistance during a first operation of the memory element and maintaining the resistance of the serial resistive element as a second resistance during a second operation of the memory element, wherein the serial resistive element includes a variable resistive element.
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公开(公告)号:US20240065001A1
公开(公告)日:2024-02-22
申请号:US18299403
申请日:2023-04-12
Applicant: SAMSUNG ELECTRONICS CO,LTD.
Inventor: Seyun KIM , Jooheon KANG , Sunho KIM , Yumin KIM , Garam PARK , Hyunjae SONG , Dongho AHN , Seungyeul YANG , Myunghun WOO , Jinwoo LEE
IPC: H10B63/00
CPC classification number: H10B63/845 , H10B63/34
Abstract: Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.
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