NEURAL NETWORK APPARATUS AND METHOD OF PROCESSING VARIABLE-RESOLUTION OPERATION BY THE SAME

    公开(公告)号:US20230076169A1

    公开(公告)日:2023-03-09

    申请号:US17987369

    申请日:2022-11-15

    Abstract: A neural network apparatus that is configured to process an operation includes neural network circuitry configured to receive a first input of an n-bit activation, store a second input of an m-bit weight, perform a determination whether to perform an operation on an ith bit of the first input and a jth bit of the second input, output an operation value of an operation performed on the ith bit of the first input and the jth bit of the second input based on the determination, and produce an operation value of the operation based on the determination.

    NEURAL NETWORK APPARATUS AND METHOD OF PROCESSING VARIABLE-RESOLUTION OPERATION BY THE SAME

    公开(公告)号:US20200242454A1

    公开(公告)日:2020-07-30

    申请号:US16557182

    申请日:2019-08-30

    Abstract: A neural network apparatus that is configured to process an operation includes neural network circuitry configured to receive a first input of an n-bit activation, store a second input of an m-bit weight, perform a determination whether to perform an operation on an ith bit of the first input and a jth bit of the second input, output an operation value of an operation performed on the ith bit of the first input and the jth bit of the second input based on the determination, and produce an operation value of the operation based on the determination.

    RESISTIVE MEMORY DEVICE HAVING MEMORY CELL ARRAY AND SYSTEM INCLUDING THE SAME

    公开(公告)号:US20190325933A1

    公开(公告)日:2019-10-24

    申请号:US16195199

    申请日:2018-11-19

    Abstract: A resistive memory device includes a memory cell array in which a plurality of memory cells are arranged. Each of the plurality of memory cells includes a variable resistor comprising a first end connected to a bit line, and a second end, a row transistor connected between a row source line and the second end of the variable resistor, the row transistor being selectable by a row word line, and a column transistor connected between a column source line and the second end of the variable resistor, the column transistor being selectable by a column word line. Based on the row transistor being selected, first data is written or second data is read in a row direction of the memory cell array, and based on the column transistor being selected, the first data is written or the second data is read in a column direction of the memory cell array.

    METHOD FOR ADAPTIVELY CONTROLLING LOW POWER DISPLAY MODE AND ELECTRONIC DEVICE THEREOF

    公开(公告)号:US20190259323A1

    公开(公告)日:2019-08-22

    申请号:US16282947

    申请日:2019-02-22

    Abstract: An electronic device includes a touch screen display including an organic light emitting layer that is formed of a plurality of pixels, a wireless communication circuit, a processor operatively coupled with the display and the wireless communication circuit, and a memory operatively coupled with the processor. The memory stores instructions that, upon execution, enable the processor to provide a first mode of displaying a first graphical user interface (GUI) on the display by using a first number of colors in a state where all the pixels are turned on, a second mode of displaying a second GUI on the display by using a second number of colors in a state where some of the pixels are turned off, and a third mode of displaying a third GUI on the display by using the first number of colors in a state where some of the pixels are turned off, and select one of the first mode, the second mode or the third mode on the basis of at least one of a state of the electronic device, a content of the GUI or a use pattern of a user.

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