公开(公告)号：US20250098171A1

公开(公告)日：2025-03-20

申请号：US18885031

申请日：2024-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghun KIM ,  Hoseok HEO ,  Sunho KIM ,  Seungyeul YANG ,  Minhyun LEE ,  Seokhoon CHOI

IPC: H10B43/30 ,  H10B43/27

Abstract: A memory device includes: a channel layer; a gate electrode spaced apart from the channel layer; and a multilayer charge trap layer disposed between the channel layer and the gate electrode, wherein the multilayer charge trap layer includes silicon oxynitride, the silicon oxynitride including gallium or silicon nitride including gallium.

公开(公告)号：US20240224530A1

公开(公告)日：2024-07-04

申请号：US18215533

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungdam HYUN ,  Kyunghun KIM ,  Sunho KIM ,  Hyungyung KIM ,  Kwangmin PARK ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI ,  Hoseok HEO

IPC: H10B43/35 ,  G11C16/04 ,  H01L29/423 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H01L29/4234 ,  H10B43/10 ,  H10B43/27

Abstract: A vertical NAND flash memory device includes a plurality of cell arrays, where each cell array of the plurality of cell arrays includes a channel layer, a charge trap layer provided on the channel layer, the charge trap layer including a matrix comprising a dielectric and a charge trap material in the matrix and including anti-ferroelectric nanocrystals or ferroelectric nanocrystals, and a plurality of gate electrodes provided on the charge trap layer.

公开(公告)号：US20240221834A1

公开(公告)日：2024-07-04

申请号：US18357407

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok HEO ,  Hyungyung KIM ,  Seungdam HYUN ,  Kyunghun KIM ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI

IPC: G11C16/04 ,  H10B43/27

CPC classification number: G11C16/0483 ,  H10B43/27

Abstract: A vertical non-volatile memory device and an electronic apparatus including the vertical non-volatile memory device are provided. The vertical non-volatile memory device includes a pillar, a channel layer surrounding a side surface of the pillar, a charge tunneling layer surrounding a side surface of the channel layer, a charge trap layer surrounding a side surface of the charge tunneling layer and including an amorphous oxynitride, a charge blocking layer surrounding a side surface of the charge trap layer, and a plurality of separation layers and a plurality of gate electrodes surrounding a side surface of the charge blocking layer and alternately arranged along the side surface of the charge blocking layer.

公开(公告)号：US20230093892A1

公开(公告)日：2023-03-30

申请号：US17685942

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin KIM ,  Doyoon KIM ,  Seyun KIM ,  Hyunjae SONG ,  Seungyeul YANG

IPC: H01L27/24 ,  H01L45/00

Abstract: Disclosed are a memory device including a vertical stack structure, a method of manufacturing the same, and/or an electronic device including the memory device. The memory device including a vertical stack structure includes an oxygen scavenger layer on a base substrate, a recording material layer on the oxygen scavenger layer and in direct contact with the oxygen scavenger layer, a channel layer on the recording material layer, a gate insulating layer on the channel layer, and a gate electrode on the gate insulating layer. The oxygen scavenger layer includes an element that forms oxygen vacancies in the recording material layer and does not include oxygen.

公开(公告)号：US20250063742A1

公开(公告)日：2025-02-20

申请号：US18805219

申请日：2024-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yumin KIM ,  Seyun KIM ,  Garam PARK ,  Hyunjae SONG ,  Seungyeul YANG ,  Seungdam Seungdam

IPC: H10B63/00

Abstract: A variable resistance memory device includes a channel layer, a resistance change layer provided on the channel layer, the resistance change layer having resistance characteristics that change based on an applied voltage and having a first oxygen diffusion activation energy, and an interface layer provided between the channel layer and the resistance change layer, the interface layer having a second oxygen diffusion activation energy that is greater than the first oxygen diffusion activation energy of the resistance change layer.

公开(公告)号：US20240215249A1

公开(公告)日：2024-06-27

申请号：US18322365

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghun KIM ,  Sunho KIM ,  Seyun KIM ,  Hyungyung KIM ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI ,  Hoseok HEO

IPC: H10B43/35 ,  H10B43/27

CPC classification number: H10B43/35 ,  H10B43/27

Abstract: A vertical NAND flash memory device may include a plurality of cell arrays. Each of the plurality of cell arrays may include a channel layer, a charge trap layer on the channel layer, and a plurality of gate electrodes on the charge trap layer. The charge trap layer may include silicon oxynitride comprising a metal. The metal may include at least one of Ga or In.

公开(公告)号：US20240196763A1

公开(公告)日：2024-06-13

申请号：US18214755

申请日：2023-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yumin KIM ,  Seyun KIM ,  Garam PARK ,  Hyunjae SONG ,  Seungyeul YANG ,  Seungdam HYUN ,  Jooheon KANG ,  Jinwoo LEE

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/826 ,  H10B63/84 ,  H10N70/8833

Abstract: A variable resistance memory device includes a pillar, a resistance change layer provided at a side surface of the pillar, a semiconductor layer provided at a side surface of the resistance change layer, a gate insulating layer provided at a side surface of the semiconductor layer, a plurality of isolating layers and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer, and an internal resistance layer between the resistance change layer and the semiconductor layer, where a resistance of the internal resistance layer is greater than a resistance of the semiconductor layer when the semiconductor layer includes conductor characteristics and the resistance of the internal resistance layer is less than the resistance of the semiconductor layer when the semiconductor layer includes insulator characteristics.

公开(公告)号：US20250029656A1

公开(公告)日：2025-01-23

申请号：US18774249

申请日：2024-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin KIM ,  Seyun KIM ,  Garam PARK ,  Hyunjae SONG ,  Seungyeul YANG ,  Seungdam HYUN

IPC: G11C13/00

Abstract: A memory device including a variable serial resistive element having a voltage dividing effect and an operating method thereof are disclosed. The memory device includes a memory unit, a variable serial resistive element connected to the memory unit, a controller connected to the variable serial resistive element and configured to control a resistance of the variable serial resistive element, and a power source connected to the variable serial resistive element. The operating method of the memory device includes maintaining a resistance of a serial resistive element connected to a memory element as a first resistance during a first operation of the memory element and maintaining the resistance of the serial resistive element as a second resistance during a second operation of the memory element, wherein the serial resistive element includes a variable resistive element.

公开(公告)号：US20240065001A1

公开(公告)日：2024-02-22

申请号：US18299403

申请日：2023-04-12

Applicant: SAMSUNG ELECTRONICS CO,LTD.

Inventor： Seyun KIM ,  Jooheon KANG ,  Sunho KIM ,  Yumin KIM ,  Garam PARK ,  Hyunjae SONG ,  Dongho AHN ,  Seungyeul YANG ,  Myunghun WOO ,  Jinwoo LEE

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.

公开(公告)号：US20230121581A1

公开(公告)日：2023-04-20

申请号：US17741847

申请日：2022-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Doyoon KIM ,  Yumin KIM ,  Hyunjae SONG ,  Seungyeul YANG

IPC: H01L27/24

Abstract: A variable resistance memory device includes: a supporting layer including an insulating material; a variable resistance layer on the supporting layer and including a first layer including a metal oxide and metal nanoparticles, the variable resistance layer including a second layer on the first layer and including an oxide; a channel layer on the variable resistance layer; a gate insulating layer on the channel layer; and a gate electrode on the gate insulating layer. The metal nanoparticles in the variable resistance layer include a first metal capable of combining with oxygen ions of the metal oxide, thereby increasing oxygen vacancies.