公开(公告)号：US20240215249A1

公开(公告)日：2024-06-27

申请号：US18322365

申请日：2023-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghun KIM ,  Sunho KIM ,  Seyun KIM ,  Hyungyung KIM ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI ,  Hoseok HEO

IPC: H10B43/35 ,  H10B43/27

CPC classification number: H10B43/35 ,  H10B43/27

Abstract: A vertical NAND flash memory device may include a plurality of cell arrays. Each of the plurality of cell arrays may include a channel layer, a charge trap layer on the channel layer, and a plurality of gate electrodes on the charge trap layer. The charge trap layer may include silicon oxynitride comprising a metal. The metal may include at least one of Ga or In.

公开(公告)号：US20210226010A1

公开(公告)日：2021-07-22

申请号：US17111965

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Minsu SEOL ,  Hyeonjin SHIN

IPC: H01L29/10 ,  H01L29/36 ,  H01L29/423

Abstract: A transistor including at least one two-dimensional (2D) channel is disclosed. A transistor according to some example embodiments includes first to third electrodes separated from each other, and a channel layer that is in contact with the first and second electrodes, parallel to the third electrode, and includes at least one 2D channel. The at least one 2D channel includes at least two regions having different doping concentrations. A transistor according to some example embodiments includes: first to third electrodes separated from each other; a 2D channel layer that is in contact with the first and second electrodes and parallel to the third electrode; a first doping layer disposed under the 2D channel layer corresponding to the first electrode; and a second doping layer disposed under the 2D channel layer corresponding to the second electrode, wherein the first and second doping layers contact the 2D channel layer.

公开(公告)号：US20210223683A1

公开(公告)日：2021-07-22

申请号：US17223568

申请日：2021-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Hyeonjin SHIN ,  Seongjun JEONG ,  Seongjun PARK

IPC: G03F1/62 ,  G03F1/64

Abstract: A pellicle configured to protecting a photomask from external contaminants may include a metal catalyst layer and a pellicle membrane including a 2D material on the metal catalyst layer, wherein the metal catalyst layer supports edge regions of the pellicle membrane and does not support a central region of the pellicle membrane. The metal catalyst layer may be on a substrate, such that the substrate and the metal catalyst layer collectively support the edge region of the pellicle membrane and do not support the central region of the pellicle membrane. The pellicle may be formed based on growing the 2D material on the metal catalyst layer and etching an inner region of the metal catalyst layer that supports the central region of the formed pellicle membrane.

公开(公告)号：US20180090317A1

公开(公告)日：2018-03-29

申请号：US15817979

申请日：2017-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Hyeonjin SHIN ,  Jaeho LEE ,  Haeryong KIM

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/778 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78 ,  H01L29/16 ,  H01L29/24 ,  H01L29/41

CPC classification number: H01L21/02568 ,  H01L21/0259 ,  H01L21/02628 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/413 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/7839 ,  H01L29/786 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78696

Abstract: An electronic device includes first and second electrodes that are spaced apart from each other and a 2D material layer. The 2D material layer connects the first and second electrodes. The 2D material layer includes a plurality of 2D nanomaterials. At least some of the 2D nanomaterials overlap one another.

公开(公告)号：US20180061490A1

公开(公告)日：2018-03-01

申请号：US15448998

申请日：2017-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Seunggeol NAM ,  Changhyun KIM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Jinseong HEO ,  Seongjun PARK

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1641

Abstract: A phase change memory device may include a phase change layer that includes a two-dimensional (2D) material. The phase change layer may include a layered structure that includes one or more layers of 2D material. The phase change layer may be provided between a first electrode and a second electrode, and the phase of at least a portion of one or more of the layers of 2D material may be changed based on an electrical signal applied to the phase change layer through the first electrode and the second electrode. The 2D material may include a chalcogenide-based material or phosphorene. The 2D material may be associated with a phase change temperature that is greater than or equal to about 200° C. and lower than or equal to about 500° C.

公开(公告)号：US20180047818A1

公开(公告)日：2018-02-15

申请号：US15439031

申请日：2017-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Minhyun LEE ,  Changhyun KIM ,  Seongjun PARK

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L21/283 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/7839 ,  H01L29/786

Abstract: A semiconductor device includes a silicon semiconductor layer including at least one region doped with a first conductive type dopant, a metal material layer electrically connected to the doped region, and a self-assembled monolayer (SAM) between the doped region and the metal material layer, the SAM forming a molecular dipole on an interface of the silicon semiconductor layer in a direction of reducing a Schottky barrier height (SBH).

公开(公告)号：US20250089341A1

公开(公告)日：2025-03-13

申请号：US18818855

申请日：2024-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok HEO ,  Minhyun LEE ,  Sangwon KIM ,  Seyun KIM ,  Seokhoon CHOI

IPC: H01L29/49 ,  G11C16/04 ,  H01L21/28 ,  H10B43/27

Abstract: A non-volatile memory device may include a channel layer extending in a first direction, a plurality of gate electrodes and a plurality of insulating layers spaced apart from the channel layer and alternately arranged in the first direction, a charge trap layer between the channel layer and the plurality of gate electrodes, and a charge tunneling layer between the channel layer and the charge trap layer. The plurality of gate electrodes may include M, A, and X, where M may include a metal; A may include a Group 13 element, a Group 14 element, or V, or a combination thereof; X may include carbon or nitrogen, and M, A, and X may be arranged to have a layered crystal structure.

公开(公告)号：US20240221834A1

公开(公告)日：2024-07-04

申请号：US18357407

申请日：2023-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoseok HEO ,  Hyungyung KIM ,  Seungdam HYUN ,  Kyunghun KIM ,  Seungyeul YANG ,  Gukhyon YON ,  Minhyun LEE ,  Seokhoon CHOI

IPC: G11C16/04 ,  H10B43/27

CPC classification number: G11C16/0483 ,  H10B43/27

Abstract: A vertical non-volatile memory device and an electronic apparatus including the vertical non-volatile memory device are provided. The vertical non-volatile memory device includes a pillar, a channel layer surrounding a side surface of the pillar, a charge tunneling layer surrounding a side surface of the channel layer, a charge trap layer surrounding a side surface of the charge tunneling layer and including an amorphous oxynitride, a charge blocking layer surrounding a side surface of the charge trap layer, and a plurality of separation layers and a plurality of gate electrodes surrounding a side surface of the charge blocking layer and alternately arranged along the side surface of the charge blocking layer.

公开(公告)号：US20230272554A1

公开(公告)日：2023-08-31

申请号：US18298692

申请日：2023-04-11

Applicant: Samsung Electronics Co., Ltd. ,  UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)

Inventor： Changseok LEE ,  Hyeonsuk SHIN ,  Hyeonjin SHIN ,  Seokmo HONG ,  Minhyun LEE ,  Seunggeol NAM ,  Kyungyeol MA

IPC: C30B29/38 ,  H01L21/02

CPC classification number: C30B29/38 ,  H01L21/02172 ,  H01L21/02252 ,  H01L21/02293

Abstract: A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

公开(公告)号：US20230079680A1

公开(公告)日：2023-03-16

申请号：US17829679

申请日：2022-06-01

Applicant: Samsung Electronics Co., Ltd. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

Inventor： Keunwook SHIN ,  Kibum KIM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Minhyun LEE ,  Changseok LEE

IPC: C01B32/186 ,  C01B32/188 ,  H01L29/41 ,  H01L29/40

Abstract: Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200° C. to about 600° C. by plasma enhanced chemical vapor deposition (PECVD).