-
公开(公告)号：US20240215249A1
公开(公告)日：2024-06-27
申请号：US18322365
申请日：2023-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghun KIM , Sunho KIM , Seyun KIM , Hyungyung KIM , Seungyeul YANG , Gukhyon YON , Minhyun LEE , Seokhoon CHOI , Hoseok HEO
Abstract: A vertical NAND flash memory device may include a plurality of cell arrays. Each of the plurality of cell arrays may include a channel layer, a charge trap layer on the channel layer, and a plurality of gate electrodes on the charge trap layer. The charge trap layer may include silicon oxynitride comprising a metal. The metal may include at least one of Ga or In.
-
公开(公告)号：US20250098171A1
公开(公告)日：2025-03-20
申请号：US18885031
申请日：2024-09-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghun KIM , Hoseok HEO , Sunho KIM , Seungyeul YANG , Minhyun LEE , Seokhoon CHOI
Abstract: A memory device includes: a channel layer; a gate electrode spaced apart from the channel layer; and a multilayer charge trap layer disposed between the channel layer and the gate electrode, wherein the multilayer charge trap layer includes silicon oxynitride, the silicon oxynitride including gallium or silicon nitride including gallium.
-
Patent Agency Ranking
公开(公告)号：US20240224530A1
公开(公告)日：2024-07-04
申请号：US18215533
申请日：2023-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungdam HYUN , Kyunghun KIM , Sunho KIM , Hyungyung KIM , Kwangmin PARK , Seungyeul YANG , Gukhyon YON , Minhyun LEE , Seokhoon CHOI , Hoseok HEO
IPC: H10B43/35 , G11C16/04 , H01L29/423 , H10B43/10 , H10B43/27
CPC classification number: H10B43/35 , G11C16/0483 , H01L29/4234 , H10B43/10 , H10B43/27
Abstract: A vertical NAND flash memory device includes a plurality of cell arrays, where each cell array of the plurality of cell arrays includes a channel layer, a charge trap layer provided on the channel layer, the charge trap layer including a matrix comprising a dielectric and a charge trap material in the matrix and including anti-ferroelectric nanocrystals or ferroelectric nanocrystals, and a plurality of gate electrodes provided on the charge trap layer.
-
公开(公告)号：US20250089341A1
公开(公告)日：2025-03-13
申请号：US18818855
申请日：2024-08-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hoseok HEO , Minhyun LEE , Sangwon KIM , Seyun KIM , Seokhoon CHOI
Abstract: A non-volatile memory device may include a channel layer extending in a first direction, a plurality of gate electrodes and a plurality of insulating layers spaced apart from the channel layer and alternately arranged in the first direction, a charge trap layer between the channel layer and the plurality of gate electrodes, and a charge tunneling layer between the channel layer and the charge trap layer. The plurality of gate electrodes may include M, A, and X, where M may include a metal; A may include a Group 13 element, a Group 14 element, or V, or a combination thereof; X may include carbon or nitrogen, and M, A, and X may be arranged to have a layered crystal structure.
-
公开(公告)号：US20240221834A1
公开(公告)日：2024-07-04
申请号：US18357407
申请日：2023-07-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hoseok HEO , Hyungyung KIM , Seungdam HYUN , Kyunghun KIM , Seungyeul YANG , Gukhyon YON , Minhyun LEE , Seokhoon CHOI
CPC classification number: G11C16/0483 , H10B43/27
Abstract: A vertical non-volatile memory device and an electronic apparatus including the vertical non-volatile memory device are provided. The vertical non-volatile memory device includes a pillar, a channel layer surrounding a side surface of the pillar, a charge tunneling layer surrounding a side surface of the channel layer, a charge trap layer surrounding a side surface of the charge tunneling layer and including an amorphous oxynitride, a charge blocking layer surrounding a side surface of the charge trap layer, and a plurality of separation layers and a plurality of gate electrodes surrounding a side surface of the charge blocking layer and alternately arranged along the side surface of the charge blocking layer.
-
公开(公告)号：US20250126803A1
公开(公告)日：2025-04-17
申请号：US18913098
申请日：2024-10-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seunggeol NAM , Sijung YOO , Minhyun LEE , Hyunjae LEE , Seokhoon CHOI
Abstract: A semiconductor device, and a memory apparatus and an electronic apparatus including the same are provided. The semiconductor device may include a gate electrode, a ferroelectric layer on the gate electrode, a channel layer on the ferroelectric layer, and a plurality of nanostructures spaced apart from each other in the ferroelectric layer. The plurality of nanostructures may be adjacent to the gate electrode or the channel layer, or a portion of the plurality of nanostructures may be adjacent to the gate electrode and the rest portion of the plurality of nanostructures may be adjacent to the channel layer.
-
公开(公告)号：US20250126802A1
公开(公告)日：2025-04-17
申请号：US18761688
申请日：2024-07-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sijung YOO , Seunggeol NAM , Donghoon KIM , Hyunjae LEE , Dukhyun CHOE , Seokhoon CHOI
Abstract: A ferroelectric field effect transistor includes a channel, a gate electrode provided to face the channel, a ferroelectric layer provided between the channel and the gate electrode, an interfacial layer provided between the channel and the ferroelectric layer, and a diffusion barrier layer provided between the ferroelectric layer and the gate electrode, wherein the diffusion barrier layer includes SiON, the diffusion barrier layer has an oxygen concentration gradient that gradually decreases from a first surface of the diffusion barrier layer facing the gate electrode toward a second surface of the diffusion barrier layer facing the ferroelectric layer, and the diffusion barrier layer may have a nitrogen concentration gradient that gradually increases from the first surface toward the second surface.
-
-
-
-
-
-
Search Results
7
records
(took 0.017 seconds)
