公开(公告)号：US20230269942A1

公开(公告)日：2023-08-24

申请号：US18096257

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myunghun WOO ,  Jooheon KANG ,  Hyunmog PARK ,  Jongho WOO ,  Suseong NOH ,  Youngji NOH

IPC: H10B43/27 ,  H10B43/40 ,  H10B43/35 ,  H10B41/27 ,  H10B41/49 ,  H10B41/35

CPC classification number: H10B43/27 ,  H10B43/40 ,  H10B43/35 ,  H10B41/27 ,  H10B41/49 ,  H10B41/35

Abstract: A semiconductor device includes a gate stack structure including alternately stacked insulating patterns and conductive patterns; a memory channel structure extending through the gate stack structure; and a bit line pad on the memory channel structure, wherein the memory channel structure includes a variable resistance layer, a channel layer surrounding the variable resistance layer, and a channel insulating layer surrounding the channel layer, and a bottom surface of the bit line pad contacts a top surface of the variable resistance layer, a top surface of the channel layer, and a top surface of the channel insulating layer.

公开(公告)号：US20230077589A1

公开(公告)日：2023-03-16

申请号：US17679863

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunmook CHOI ,  Jooheon KANG ,  Sanghoon KIM ,  Jihong KIM

IPC: H01L27/24

Abstract: A semiconductor device includes a horizontal wiring layer on a substrate, a stack structure disposed on the horizontal wiring layer and including insulating layers and electrode layers alternately stacked on each other, and a pillar structure extending into the horizontal wiring layer and extending through the stack structure. The electrode layers include one or a plurality of selection lines adjacent to an uppermost end of the stack structure, and word lines surrounding the stack structure below the one or plurality of selection lines. The pillar structure includes a variable resistive layer, a channel layer between the variable resistive layer and the stack structure, a gate dielectric layer between the channel layer and the stack structure, and a blocking pattern disposed between the variable resistive layer and the channel layer and being adjacent to a first selection line among the one or plurality of selection lines.

公开(公告)号：US20240065001A1

公开(公告)日：2024-02-22

申请号：US18299403

申请日：2023-04-12

Applicant: SAMSUNG ELECTRONICS CO,LTD.

Inventor： Seyun KIM ,  Jooheon KANG ,  Sunho KIM ,  Yumin KIM ,  Garam PARK ,  Hyunjae SONG ,  Dongho AHN ,  Seungyeul YANG ,  Myunghun WOO ,  Jinwoo LEE

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.

公开(公告)号：US20240196763A1

公开(公告)日：2024-06-13

申请号：US18214755

申请日：2023-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yumin KIM ,  Seyun KIM ,  Garam PARK ,  Hyunjae SONG ,  Seungyeul YANG ,  Seungdam HYUN ,  Jooheon KANG ,  Jinwoo LEE

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/826 ,  H10B63/84 ,  H10N70/8833

Abstract: A variable resistance memory device includes a pillar, a resistance change layer provided at a side surface of the pillar, a semiconductor layer provided at a side surface of the resistance change layer, a gate insulating layer provided at a side surface of the semiconductor layer, a plurality of isolating layers and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer, and an internal resistance layer between the resistance change layer and the semiconductor layer, where a resistance of the internal resistance layer is greater than a resistance of the semiconductor layer when the semiconductor layer includes conductor characteristics and the resistance of the internal resistance layer is less than the resistance of the semiconductor layer when the semiconductor layer includes insulator characteristics.

公开(公告)号：US20230165001A1

公开(公告)日：2023-05-25

申请号：US17989061

申请日：2022-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Jooheon KANG ,  Donggeon GU ,  Doyoon KIM ,  Yumin KIM ,  Suseong NOH ,  Changyup PARK ,  Hyunjae SONG ,  Dongho AHN ,  Myunghun WOO

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device includes a lower structure, a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction, and a channel structure in a channel hole passing through the stack structure. The channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole, the channel layer includes a first element, the variable resistance material layer includes a second element, different from the first element, oxygen, and oxygen vacancies, and the data storage material layer includes the first element, the second element, oxygen, and oxygen vacancies.