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    VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    1.
    发明公开
    VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240274212A1

    公开(公告)日：2024-08-15

    申请号：US18241621

    申请日：2023-09-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yumin KIM ,  Jungyu LEE ,  Jihyun PARK ,  Chiweon YOON ,  Eunchan LEE

    IPC: G11C29/12 ,  G11C7/04 ,  G11C29/02

    CPC classification number: G11C29/12005 ,  G11C7/04 ,  G11C29/028 ,  G11C29/1201

    Abstract: A voltage generation circuit includes a current generation circuit, a slope trimming circuit and an offset trimming circuit. The current generation circuit is connected between an input voltage node and an output node that outputs a complementary to absolute temperature (CTAT) output voltage that decreases as an operation temperature increases. The current generation circuit generates a reference current flowing through the output node, the reference current having a constant magnitude regardless of the operation temperature. The slope trimming circuit is connected between the output node and an intermediate node. The slope trimming circuit adjusts a slope of the CTAT output voltage based on a first trimming code. The offset trimming circuit is connected between the intermediate node and a ground voltage node. The offset trimming circuit configured to adjust an offset voltage of the CTAT output voltage based on a second trimming code.

    VARIABLE RESISTANCE MEMORY DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME
    5.
    发明公开
    VARIABLE RESISTANCE MEMORY DEVICE AND ELECTRONIC APPARATUS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240196763A1

    公开(公告)日：2024-06-13

    申请号：US18214755

    申请日：2023-06-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yumin KIM ,  Seyun KIM ,  Garam PARK ,  Hyunjae SONG ,  Seungyeul YANG ,  Seungdam HYUN ,  Jooheon KANG ,  Jinwoo LEE

    IPC: H10N70/00 ,  H10B63/00

    CPC classification number: H10N70/826 ,  H10B63/84 ,  H10N70/8833

    Abstract: A variable resistance memory device includes a pillar, a resistance change layer provided at a side surface of the pillar, a semiconductor layer provided at a side surface of the resistance change layer, a gate insulating layer provided at a side surface of the semiconductor layer, a plurality of isolating layers and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer, and an internal resistance layer between the resistance change layer and the semiconductor layer, where a resistance of the internal resistance layer is greater than a resistance of the semiconductor layer when the semiconductor layer includes conductor characteristics and the resistance of the internal resistance layer is less than the resistance of the semiconductor layer when the semiconductor layer includes insulator characteristics.

    MEMORY DEVICE INCLUDING VERTICAL STACK STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    MEMORY DEVICE INCLUDING VERTICAL STACK STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220310827A1

    公开(公告)日：2022-09-29

    申请号：US17459527

    申请日：2021-08-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yumin KIM ,  Doyoon KIM ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Youngjin CHO

    IPC: H01L29/68 ,  H01L27/115

    Abstract: Disclosed are a memory device including a vertical stack structure and a method of manufacturing the memory device. The memory device includes an insulating structure having a shape including a first surface and a protrusion portion protruding in a first direction from the first surface, a recording material layer covering the protrusion portion along a protruding shape of the protrusion portion and extending to the first surface on the insulating structure a channel layer on the recording material layer along a surface of the recording material layer, a gate insulating layer on the channel layer, and a gate electrode formed at a location on the gate insulating layer to face a second surface which is a protruding upper surface of the protrusion portion, wherein a void exists between the gate electrode and the insulating structure, defined by the insulating structure and the recording material layer.

    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明申请
    MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20220077235A1

    公开(公告)日：2022-03-10

    申请号：US17317154

    申请日：2021-05-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yumin KIM ,  Seyun KIM ,  Jinhong KIM ,  Soichiro MIZUSAKI ,  Youngjin CHO

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A memory device may include an insulating structure including a first surface and a protrusion portion protruding from the first surface in a first direction, a recording material layer on the insulating structure and extending along a protruding surface of the protrusion portion to cover the protrusion portion and extending onto the first surface of the insulating structure, a channel layer on the recording material layer and extending along a surface of the recording material layer, a gate insulating layer on the channel layer; and a gate electrode formed on the gate insulating layer at a location facing a second surface of the insulating structure. The second surface of the insulating structure may be a protruding upper surface of the protrusion portion.

    MEMORY DEVICE INCLUDING VARIABLE SERIAL RESISTIVE ELEMENT HAVING VOLTAGE DIVIDING EFFECT AND OPERATING METHOD THEREOF
    9.
    发明申请
    MEMORY DEVICE INCLUDING VARIABLE SERIAL RESISTIVE ELEMENT HAVING VOLTAGE DIVIDING EFFECT AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20250029656A1

    公开(公告)日：2025-01-23

    申请号：US18774249

    申请日：2024-07-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yumin KIM ,  Seyun KIM ,  Garam PARK ,  Hyunjae SONG ,  Seungyeul YANG ,  Seungdam HYUN

    IPC: G11C13/00

    Abstract: A memory device including a variable serial resistive element having a voltage dividing effect and an operating method thereof are disclosed. The memory device includes a memory unit, a variable serial resistive element connected to the memory unit, a controller connected to the variable serial resistive element and configured to control a resistance of the variable serial resistive element, and a power source connected to the variable serial resistive element. The operating method of the memory device includes maintaining a resistance of a serial resistive element connected to a memory element as a first resistance during a first operation of the memory element and maintaining the resistance of the serial resistive element as a second resistance during a second operation of the memory element, wherein the serial resistive element includes a variable resistive element.

    MEMORY DEVICE AND OPERATING METHOD THEREOF
    10.
    发明公开
    MEMORY DEVICE AND OPERATING METHOD THEREOF 审中-公开

    公开(公告)号：US20240257843A1

    公开(公告)日：2024-08-01

    申请号：US18230951

    申请日：2023-08-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD

    Inventor： Jihyun PARK ,  Jungyu LEE ,  Yumin KIM ,  Chiweon YOON ,  Eunchan LEE

    IPC: G11C7/02 ,  G11C7/10 ,  G11C7/14

    CPC classification number: G11C7/02 ,  G11C7/1057 ,  G11C7/14

    Abstract: The present disclosure provides for memory apparatuses and systems including noise cancellation circuits, and operating methods thereof. In some embodiments, a memory device includes a first pad, a memory cell plane comprising a plurality of memory cells, a page buffer circuit, and a noise cancellation circuit. The page buffer circuit is configured to sense the memory cell plane, and identify, based on the sensing of the memory cell plane, a state stored in a memory cell of the plurality of memory cells, according to a ground voltage. The noise cancellation circuit is configured to receive a first ground voltage from the first pad, determine a reference voltage based on the first ground voltage, generate a second ground voltage that offsets a noise voltage, based on the reference voltage, and output the second ground voltage to the page buffer circuit.

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