公开(公告)号：US09997596B2

公开(公告)日：2018-06-12

申请号：US15041559

申请日：2016-02-11

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu Choi ,  Jun-Young Park

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/266 ,  H01L21/308 ,  H01L29/66 ,  H01L21/306 ,  H01L29/423

CPC classification number: H01L29/0673 ,  H01L21/02694 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/3081 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66568 ,  H01L29/7391

Abstract: A tunneling field-effect transistor may be provided that includes: a substrate; a source which is formed on the substrate and into which p+ type impurity ion is injected; a drain which is formed on the substrate and into which n+ type impurity ion is injected; a plurality of vertically stacked nanowire channels which are formed on the substrate; a gate insulation layer which is formed on the plurality of nanowire channels; and a gate which is formed on the gate insulation layer. As a result, it is possible to generate a higher driving current without changing the length of the gate and the area of the channel (degree of integration).

公开(公告)号：US10956622B2

公开(公告)日：2021-03-23

申请号：US16032630

申请日：2018-07-11

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu Choi ,  Jun-Young Park

IPC: G06F21/79 ,  G11C13/00 ,  G11C16/34 ,  H05B3/00 ,  G11C16/22 ,  G11C16/30 ,  G11C11/16 ,  G11C16/14 ,  G11C7/04 ,  G11C16/10 ,  H05B3/26 ,  H01L23/34

Abstract: The present invention provides a thermal hardware-based data security device that is capable of physically, hardware-wise, and permanently erasing data stored in a memory and of enabling a storage device to be reused, and a method thereof. The thermal hardware-based data security device includes: a memory chip capable of storing data; a heater module which supplies heat to permanently erase the data stored in a memory cell within the memory chip; and a switch module which short-circuits the heater module between a power supply unit and a ground when switched on, and thus, controls the heater module to be operated.

公开(公告)号：US09728539B2

公开(公告)日：2017-08-08

申请号：US15044702

申请日：2016-02-16

Applicant: Korea Advanced Institute of Science And Technology

Inventor： Yang-Kyu Choi ,  Jun-Young Park ,  Byung-Hyun Lee ,  Dae-Chul Ahn

IPC: G11C11/24 ,  H01L27/108 ,  H01L29/06 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L21/265 ,  H01L21/308 ,  H01L21/02 ,  H01L29/423 ,  G11C11/409 ,  G11C7/10

CPC classification number: H01L27/10802 ,  G11C7/1072 ,  G11C11/404 ,  G11C11/409 ,  G11C11/565 ,  G11C2211/4016 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3083 ,  H01L29/0673 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/66439

Abstract: A multi-bit capacitorless DRAM according to the embodiment of the present invention may be provided that includes: a substrate; a source and a drain formed on the substrate; a plurality of nanowire channels formed on the substrate; a gate insulation layer formed in the plurality of nanowire channels; and a gate formed on the gate insulation layer. Two or more nanowire channels among the plurality of nanowire channels have different threshold voltages. Each of the nanowire channels includes: a silicon layer; a first epitaxial layer which is formed to surround the silicon layer; and a second epitaxial layer which is formed to surround the first epitaxial layer. As a result, the high integration multi-bit capacitorless DRAM which operates at multi-bits can be implemented and a performance of accumulating excess holes can be improved by using energy band gap.

公开(公告)号：US20190393237A1

公开(公告)日：2019-12-26

申请号：US16175480

申请日：2018-10-30

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Jun-Young Park

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/367 ,  H01L23/373

Abstract: Disclosed are a vertically-integrated 3-dimensional flash memory for improving a reliability of cells and a fabrication method thereof. The fabrication method of the vertically-integrated 3-dimensional flash memory includes sequentially stacking a first insulating layer and a second insulating layer on a substrate to form a plurality of insulating layers, etching a portion of the insulating layers to expose an area of the substrate, forming a channel layer on a side surface of the etched insulating layers and on the substrate, forming a first macaroni layer on the channel layer, and forming a second macaroni layer on the first macaroni layer such that a side surface and a lower surface of the second macaroni layer are surrounded by the first macaroni layer.

公开(公告)号：US10084128B2

公开(公告)日：2018-09-25

申请号：US15426719

申请日：2017-02-07

Applicant: Korea Advanced Institute of Science And Technology ,  CENTER FOR INTEGRATED SMART SENSORS FOUNDATION

Inventor： Yang-Kyu Choi ,  Jun-Young Park ,  Chang-Hoon Jeon

IPC: H01L29/06 ,  H03H9/24 ,  H01L29/775 ,  H01L21/762 ,  H01L27/088 ,  G11C16/04 ,  H01L27/11 ,  H01L21/74 ,  H01L29/78 ,  H01L29/792 ,  H01L45/00 ,  H01L29/423 ,  H03K17/687

CPC classification number: H01L45/1206 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L45/1226 ,  H03K17/687

Abstract: Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.

公开(公告)号：US20180102477A1

公开(公告)日：2018-04-12

申请号：US15426719

申请日：2017-02-07

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Jun-Young Park ,  Chang-Hoon Jeon

IPC: H01L45/00 ,  H01L29/06 ,  H01L29/423 ,  H03K17/687

CPC classification number: H01L45/1206 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L35/00 ,  H01L45/1226 ,  H03K17/687

Abstract: Provided is a method for increasing a driving current of a junctionless transistor that includes: a substrate; a source region and a drain region which are formed on the substrate and are doped with the same type of dopant; a nanowire channel region which connects the source region and the drain source and is doped with the same type dopant as that of the source region and the drain region; a gate insulation layer which is formed to surround the nanowire channel region; and a gate electrode which is formed on the gate insulation layer and is formed to surround the nanowire channel region. An amount of current flowing through the nanowire channel region is increased by joule heat generated by applying a voltage to the source region and the drain region.