公开(公告)号：US09424927B2

公开(公告)日：2016-08-23

申请号：US14187668

申请日：2014-02-24

Applicant: Kabushiki Kaisha Toshiba

Inventor： Jiezhi Chen ,  Tetsufumi Tanamoto ,  Yuichiro Mitani ,  Takao Marukame

IPC: G11C16/00 ,  G11C16/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/06 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3495

Abstract: A memory system according to an embodiment may have an integration unit and a prediction unit. The integration unit may detect substrate current flowing through a substrate of a non-volatile memory when the non-volatile memory with a memory cell which has binary or multivalued being the binary or more is written/erased. The integration unit may records an integration value of the detected substrate current into a storage. The prediction unit may predict a lifetime of the non-volatile memory based on the integration value which is recorded on the storage.

Abstract translation: 根据实施例的存储器系统可以具有集成单元和预测单元。 当具有二进制或多值的二进制或多值的存储单元的非易失性存储器被写/擦除时，积分单元可以检测流过非易失性存储器的衬底的衬底电流。 积分单元可以将检测到的衬底电流的积分值记录到存储器中。 预测单元可以基于记录在存储器上的积分值来预测非易失性存储器的寿命。

公开(公告)号：US20160179431A1

公开(公告)日：2016-06-23

申请号：US15056133

申请日：2016-02-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Jiezhi CHEN ,  Yuuichiro Mitani ,  Tetsufumi Tanamoto ,  Takao Marukame

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0688 ,  G06F21/73 ,  H04L9/0866 ,  H04L9/3278

Abstract: An individual identification device (1) according to embodiments may identify a storage device (100) including one or more memory chips (40). The device comprises a first storage (40), a region allocator (15), and a hardware fingerprint generator (12). The first storage may be configured to store write data. The region allocator may be configured to write the write data in a specific region in each memory chip. The hardware fingerprint generator may be configured to generate hardware fingerprint data based on mismatch bits between the write data and read data read out from the specific region in each memory chip.

Abstract translation: 根据实施例的个人识别装置（1）可以标识包括一个或多个存储器芯片（40）的存储装置（100）。 该设备包括第一存储器（40），区域分配器（15）和硬件指纹生成器（12）。 第一存储器可以被配置为存储写入数据。 区域分配器可以被配置为将写入数据写入每个存储器芯片中的特定区域。 硬件指纹生成器可以被配置为基于写入数据和从每个存储器芯片中的特定区域读出的读取数据之间的失配比特来生成硬件指纹数据。

公开(公告)号：US08981436B2

公开(公告)日：2015-03-17

申请号：US14041055

申请日：2013-09-30

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yoshiaki Saito ,  Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Tetsufumi Tanamoto

IPC: H01L21/02 ,  H01L27/108 ,  H01L29/94 ,  H01L29/82 ,  H01L21/00 ,  H01L43/10 ,  H01L29/66 ,  H03K19/173 ,  H03K19/18 ,  H03K19/177

CPC classification number: H01L43/10 ,  H01L29/66984 ,  H03K19/1733 ,  H03K19/17728 ,  H03K19/18

Abstract: A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.

Abstract translation: 根据实施例的堆叠结构包括：半导体层; 形成在所述半导体层上的第一层，所述第一层含有选自Zr，Ti和Hf中的至少一种元素，所述第一层不比单原子层薄，并且不比五原子层厚; 形成在所述第一层上的隧道势垒层; 以及形成在隧道势垒层上的磁性层。

公开(公告)号：US20140143292A1

公开(公告)日：2014-05-22

申请号：US14086389

申请日：2013-11-21

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Shinichi YASUDA ,  Tetsufumi Tanamoto ,  Noriko Inoue ,  Akira Tomita ,  Ryusuke Murakami ,  Atsushi Shimbo

IPC: G06F7/58

CPC classification number: G06F7/588 ,  G06F7/58 ,  G06F7/582 ,  G06F7/584

Abstract: According to one embodiment, a random number generating circuit includes first to N-th oscillating circuits (N is a natural number equal to 2 or greater), first to N-th latch circuits that latch outputs of the first to N-th oscillating circuits by a first clock having a first frequency, first to N-th exclusive OR circuits, (N+1)-th to (2×N)-th latch circuits that latch outputs of the first to N-th exclusive OR circuits by the first clock, an (N+1)-th exclusive OR circuit that outputs an exclusive OR of outputs of the (N+1)-th to (2×N)-th latch circuits, and an M-bit shift register that converts serial data output from the (N+1)-th exclusive OR circuit into M-bit parallel data (M is a natural number equal to 2 or greater) by a second clock having a second frequency.

Abstract translation: 根据一个实施例，随机数产生电路包括第一至第N振荡电路（N为等于2或更大的自然数），锁存第一至第N振荡电路的第一至第N锁存电路 通过具有第一频率，第一至第N异或电路的第一时钟，（N + 1）至第（2×N）个锁存电路，其锁存第一至第N异或电路的输出 第一时钟，输出第（N + 1）〜（2×N）个锁存电路的输出的异或的第（N + 1）异或电路，以及M位移位寄存器， 通过具有第二频率的第二时钟从第（N + 1）异或电路输出到M位并行数据（M为等于2或更大的自然数）的串行数据。

公开(公告)号：US09460316B2

公开(公告)日：2016-10-04

申请号：US14190463

申请日：2014-02-26

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tetsufumi Tanamoto ,  Takao Marukame ,  Shinichi Yasuda ,  Yuichiro Mitani ,  Atsushi Shimbo ,  Tatsuya Kishi

IPC: G06F12/14 ,  G06F21/73 ,  G11C11/16 ,  G11C13/00 ,  G11C16/10 ,  G11C16/34 ,  G11C7/24

CPC classification number: G06F21/73 ,  G11C7/24 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  G11C13/0035 ,  G11C16/10 ,  G11C16/349

Abstract: According to an embodiment, an authentication device includes an acquiring unit, a predicting unit, and an authenticating unit. The acquiring unit is configured to acquire performance information of a first device that is a device to be authenticated. The predicting unit is configured to predict performance information of a second device that is a device being a reference for authentication according to a change with time from initial performance information. The authenticating unit is configured to perform an authentication process of determining whether or not the first device falls into the second device on a basis of a degree of agreement between the performance information acquired by the acquiring unit and the performance information predicted by the predicting unit.

Abstract translation: 根据实施例，认证装置包括获取单元，预测单元和认证单元。 获取单元被配置为获取作为要认证的设备的第一设备的性能信息。 预测单元被配置为根据与初始性能信息随时间的变化来预测作为用于认证的参考的设备的第二设备的性能信息。 认证单元被配置为基于由获取单元获取的演奏信息与由预测单元预测的演奏信息之间的一致性来执行确定第一设备是否落入第二设备的认证处理。

公开(公告)号：US20160196861A1

公开(公告)日：2016-07-07

申请号：US15067586

申请日：2016-03-11

Applicant: Kabushiki Kaisha Toshiba

Inventor： Hideyuki SUGIYAMA ,  Tetsufumi Tanamoto ,  Mizue Ishikawa ,  Tomoaki Inokuchi ,  Yoshiaki Saito

IPC: G11C11/16

CPC classification number: G11C11/165 ,  G11C11/161 ,  G11C11/1675 ,  G11C2013/0071 ,  H01L27/228 ,  H01L43/08 ,  H03K19/16

Abstract: A magnetic memory includes a magnetoresistive device and a load resistance unit. The magnetoresistive device has a first resistance state and a second resistance state and includes a first ferromagnetic layer and a second ferromagnetic layer. The load resistance unit is electrically connected to the magnetoresistive device. The load resistance unit is in a first state and a second state. Differential resistance of the load resistance unit at the second state is lower than differential resistance of the load resistance unit at the first state.

Abstract translation: 磁存储器包括磁阻器件和负载电阻单元。 磁阻器件具有第一电阻状态和第二电阻状态，并且包括第一铁磁层和第二铁磁层。 负载电阻单元电连接到磁阻器件。 负载电阻单元处于第一状态和第二状态。 负载电阻单元在第二状态下的差分电阻低于负载电阻单元在第一状态下的差分电阻。

公开(公告)号：US09171888B2

公开(公告)日：2015-10-27

申请号：US14445331

申请日：2014-07-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Michael Arnaud Quinsat ,  Tetsufumi Tanamoto ,  Shiho Nakamura

IPC: G11C11/00 ,  H01L27/22 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L27/228 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C19/0841 ,  H01L27/222 ,  H01L43/02

Abstract: According to one embodiment, a magnetic memory device includes a magnetic unit, a switching part, and a reading part. The magnetic unit includes a magnetic wire, and first and second magnetic parts. The magnetic wire includes magnetic domains and has one end and one other end. The first magnetic part is connected with the one end and has a first magnetization. The second magnetic part is connected with the one end, and has a second magnetization. The switching part includes first and second switches. The first switch is connected with the first magnetic part and flows a first current between the first magnetic part and the magnetic wire. The second switch is connected with the second magnetic part and flows a second current between the second magnetic part and the magnetic wire. The reading part is configured to read a magnetization of the magnetic domains.

Abstract translation: 根据一个实施例，磁存储器件包括磁性单元，开关部件和读取部件。 磁性单元包括磁线，以及第一和第二磁性部分。 磁线包括磁畴并具有一端和另一端。 第一磁性部分与一端连接并具有第一磁化。 第二磁性部分与一端连接，并具有第二磁化强度。 开关部分包括第一和第二开关。 第一开关与第一磁性部分连接，并且在第一磁性部分和电磁线之间流动第一电流。 第二开关与第二磁性部分连接，并在第二磁性部分和磁性线之间流动第二电流。 读取部分被配置为读取磁畴的磁化。

公开(公告)号：US20140117427A1

公开(公告)日：2014-05-01

申请号：US14041055

申请日：2013-09-30

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yoshiaki SAITO ,  Tomoaki Inokuchi ,  Mizue Ishikawa ,  Hideyuki Sugiyama ,  Tetsufumi Tanamoto

IPC: H01L43/10

CPC classification number: H01L43/10 ,  H01L29/66984 ,  H03K19/1733 ,  H03K19/17728 ,  H03K19/18

Abstract: A stacked structure according to an embodiment includes: a semiconductor layer; a first layer formed on the semiconductor layer, the first layer containing at least one element selected from Zr, Ti, and Hf, the first layer being not thinner than a monoatomic layer and not thicker than a pentatomic layer; a tunnel barrier layer formed on the first layer; and a magnetic layer formed on the tunnel barrier layer.

Abstract translation: 根据实施例的堆叠结构包括：半导体层; 形成在所述半导体层上的第一层，所述第一层含有选自Zr，Ti和Hf中的至少一种元素，所述第一层不比单原子层薄，并且不比五原子层厚; 形成在所述第一层上的隧道势垒层; 以及形成在隧道势垒层上的磁性层。

公开(公告)号：US11586887B2

公开(公告)日：2023-02-21

申请号：US16556362

申请日：2019-08-30

Applicant: Kabushiki Kaisha Toshiba

Inventor： Takao Marukame ,  Tetsufumi Tanamoto ,  Yoshifumi Nishi ,  Kumiko Nomura

IPC: G06N3/063

Abstract: According to an embodiment, a neural network apparatus includes a plurality of neuron circuits, each including an integration circuit, a firing circuit, and a secondary battery. The integration circuit is configured to output an integral signal obtained by integrating input signals. The firing circuit is configured to generate, in accordance with the integral signal, a pulse signal to be transmitted to the neuron circuit provided at a subsequent layer. The secondary battery is configured to supply the firing circuit with drive electric power used for generating the pulse signal.

公开(公告)号：US09712166B2

公开(公告)日：2017-07-18

申请号：US15068794

申请日：2016-03-14

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tetsufumi Tanamoto ,  Shinichi Yasuda ,  Shinobu Fujita

IPC: H03K17/00 ,  G06F7/58 ,  H03K19/003

CPC classification number: H03K19/003 ,  G06F7/588 ,  G09C1/00 ,  H03K3/0315 ,  H03K3/84 ,  H04L9/3278

Abstract: A data generating device according to embodiments comprises a ring oscillator, a flip-flop circuit and a generator. The flip-flop circuit includes a first terminal and a second terminal to each of which the ring oscillator output is inputted, and that determines a value of output of the ring oscillator. The generator generates an ID for authentication based on one or more values determined by the flip-flop circuit at the time when the ring oscillator is turned on.