公开(公告)号：US10755984B2

公开(公告)日：2020-08-25

申请号：US15576396

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Ying Pang ,  Nabil G. Mistkawi ,  Anand S. Murthy ,  Tahir Ghani ,  Huang-Lin Chao

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.

公开(公告)号：US20210020632A1

公开(公告)日：2021-01-21

申请号：US17032069

申请日：2020-09-25

Applicant: INTEL CORPORATION

Inventor： Nabil G. Mistkawi ,  Glenn A. Glass

IPC: H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 11 nanometers, fin height is greater than 155 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. An integrated circuit device with a substrate and a plurality of fins is provided where fin width is less than 15 nanometers, fin height is greater than 190 nanometers and spacing between any two neighboring fins is less than 30 nanometers and each fin is in non-collapsed state. A method for forming a fin-based transistor structure is provided where a plurality of fins on a substrate are pre-treated with at least one of a self-assembled monolayer, a non-polar solvent, and a surfactant. One or more of these treatments is to reduce adhesion and/or cohesive forces to prevent occurrence of fin collapse.

公开(公告)号：US09472456B2

公开(公告)日：2016-10-18

申请号：US14140085

申请日：2013-12-24

Applicant: Intel Corporation

Inventor： Erica J. Thompson ,  Nabil G. Mistkawi ,  Rohit Grover

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L21/76897 ,  H01L21/32115 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76865

Abstract: Methods for selectively etching titanium and titanium nitride are disclosed. In some embodiments the method involve exposing a workpiece to a first solution to remove titanium nitride, exposing the workpiece to a second solution to remove titanium, and exposing the workpiece to a third solution to remove residual titanium nitride, if any. The solutions are formulated such that they may selectively remove titanium and/or titanium nitride, while not etching or not substantially etching certain other materials such as dielectric materials, oxides, and metals other than titanium.

Abstract translation: 公开了选择性蚀刻钛和氮化钛的方法。 在一些实施方案中，该方法包括将工件暴露于第一溶液以除去氮化钛，将工件暴露于第二溶液以除去钛，并将工件暴露于第三溶液以除去残留的氮化钛（如果有的话）。 这些溶液被配制成使得它们可以选择性地除去钛和/或氮化钛，同时不蚀刻或基本不蚀刻某些其他材料，例如电介质材料，氧化物和钛以外的金属。

公开(公告)号：US10541334B2

公开(公告)日：2020-01-21

申请号：US16199445

申请日：2018-11-26

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani ,  Ying Pang ,  Nabil G. Mistkawi

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/161 ,  H01L21/762 ,  H01L27/092 ,  H01L29/167 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US09859424B2

公开(公告)日：2018-01-02

申请号：US15116453

申请日：2014-03-21

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani ,  Ying Pang ,  Nabil G. Mistkawi

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/8238 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L27/092 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US10833076B2

公开(公告)日：2020-11-10

申请号：US16327033

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Nabil G. Mistkawi ,  Glenn A. Glass

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/08 ,  H01L29/423

Abstract: An integrated circuit device with a substrate and a plurality of fins is provided where the fin width is less than 11 nanometers, the fin height is greater than 155 nanometers and the spacing between any two neighboring fins is less than 30 nanometers and each of the fins is in a non-collapsed state. An integrated circuit device with a substrate and a plurality of fins is also provided where the fin width is less than 15 nanometers, the fin height is greater than 190 nanometers and the spacing between any two neighboring fins is less than 30 nanometers and each of the fins is in a non-collapsed state. A method for forming a fin-based transistor structure is also provided where a plurality of fins on a substrate are pre-treated with at least one of a self-assembled monolayer, a non-polar solvent, and a surfactant. One or more of these treatments is provided to reduce the adhesion and/or cohesive forces to prevent the occurrence of fin collapse.

公开(公告)号：US20190221641A1

公开(公告)日：2019-07-18

申请号：US16327034

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Nabil G. Mistkawi ,  Karthik Jambunathan ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02527 ,  H01L21/02532 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/06 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/66 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/785

Abstract: Techniques are disclosed for forming nanowire transistors employing carbon-based layers. Carbon is added to the sacrificial layers and/or non-sacrificial layers of a multilayer stack forming one or more nanowires in the transistor channel region. Such carbon-based layers reduce or prevent diffusion and intermixing of the sacrificial and non-sacrificial portions of the multilayer stack. The reduction of diffusion/intermixing can allow for the originally formed layers to effectively maintain their original thicknesses, thereby enabling the formation of relatively more nanowires for a given channel region height because of the more accurate processing scheme. The techniques can be used to benefit group IV semiconductor material nanowire devices (e.g., devices including Si, Ge, and/or SiGe) and can also assist with the selective etch processing used to form the nanowires. The carbon concentration of the sacrificial and/or non-sacrificial layers can be adjusted to facilitate etch process to liberate nanowires in the channel region.

公开(公告)号：US10147817B2

公开(公告)日：2018-12-04

申请号：US15860292

申请日：2018-01-02

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Tahir Ghani ,  Ying Pang ,  Nabil G. Mistkawi

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L21/8238 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L27/092 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786 ,  H01L29/161

Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.

公开(公告)号：US11538905B2

公开(公告)日：2022-12-27

申请号：US16327034

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Nabil G. Mistkawi ,  Karthik Jambunathan ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/165

Abstract: Techniques are disclosed for forming nanowire transistors employing carbon-based layers. Carbon is added to the sacrificial layers and/or non-sacrificial layers of a multilayer stack forming one or more nanowires in the transistor channel region. Such carbon-based layers reduce or prevent diffusion and intermixing of the sacrificial and non-sacrificial portions of the multilayer stack. The reduction of diffusion/intermixing can allow for the originally formed layers to effectively maintain their original thicknesses, thereby enabling the formation of relatively more nanowires for a given channel region height because of the more accurate processing scheme. The techniques can be used to benefit group IV semiconductor material nanowire devices (e.g., devices including Si, Ge, and/or SiGe) and can also assist with the selective etch processing used to form the nanowires. The carbon concentration of the sacrificial and/or non-sacrificial layers can be adjusted to facilitate etch process to liberate nanowires in the channel region.

公开(公告)号：US10944006B2

公开(公告)日：2021-03-09

申请号：US16070262

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Chandra S. Mohapatra ,  Hei Kam ,  Nabil G. Mistkawi ,  Jun Sung Kang ,  Biswajeet Guha

IPC: H01L21/308 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8258

Abstract: A trench is formed in an insulating layer to expose a native fin on a substrate. A replacement fin is deposited on the native fin in the trench. The replacement fin is trimmed laterally.