Invention Application
- Patent Title: NANOWIRE TRANSISTORS EMPLOYING CARBON-BASED LAYERS
-
Application No.: US16327034Application Date: 2016-09-30
-
Publication No.: US20190221641A1Publication Date: 2019-07-18
- Inventor: Glenn A. Glass , Anand S. Murthy , Nabil G. Mistkawi , Karthik Jambunathan , Tahir Ghani
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- International Application: PCT/US2016/054708 WO 20160930
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/165 ; H01L29/78 ; H01L29/10 ; H01L29/08 ; H01L29/66 ; H01L21/8234 ; H01L21/02

Abstract:
Techniques are disclosed for forming nanowire transistors employing carbon-based layers. Carbon is added to the sacrificial layers and/or non-sacrificial layers of a multilayer stack forming one or more nanowires in the transistor channel region. Such carbon-based layers reduce or prevent diffusion and intermixing of the sacrificial and non-sacrificial portions of the multilayer stack. The reduction of diffusion/intermixing can allow for the originally formed layers to effectively maintain their original thicknesses, thereby enabling the formation of relatively more nanowires for a given channel region height because of the more accurate processing scheme. The techniques can be used to benefit group IV semiconductor material nanowire devices (e.g., devices including Si, Ge, and/or SiGe) and can also assist with the selective etch processing used to form the nanowires. The carbon concentration of the sacrificial and/or non-sacrificial layers can be adjusted to facilitate etch process to liberate nanowires in the channel region.
Public/Granted literature
- US11538905B2 Nanowire transistors employing carbon-based layers Public/Granted day:2022-12-27
Information query
IPC分类: