Invention Grant
- Patent Title: Techniques for integration of Ge-rich p-MOS source/drain
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Application No.: US16199445Application Date: 2018-11-26
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Publication No.: US10541334B2Publication Date: 2020-01-21
- Inventor: Glenn A. Glass , Anand S. Murthy , Tahir Ghani , Ying Pang , Nabil G. Mistkawi
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L21/8238 ; H01L29/66 ; H01L29/161 ; H01L21/762 ; H01L27/092 ; H01L29/167 ; H01L29/45 ; H01L29/423 ; H01L29/786 ; B82Y10/00 ; H01L29/775 ; H01L29/06 ; H01L29/417 ; H01L29/165 ; H01L21/02 ; H01L21/306 ; H01L29/08

Abstract:
Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm−3.
Public/Granted literature
- US20190109234A1 TECHNIQUES FOR INTEGRATION OF GE-RICH P-MOS SOURCE/DRAIN Public/Granted day:2019-04-11
Information query
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