公开(公告)号：US09704798B2

公开(公告)日：2017-07-11

申请号：US14137497

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Sridhar Govindaraju ,  Anindya Dasgupta ,  Rohit Grover

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment includes a metal interconnect structure, comprising: a dielectric layer on a substrate; an opening in the dielectric layer, wherein the opening has opening sidewalls and exposes a conductive region of at least one of the substrate and an additional interconnect structure; a first atomic layer deposition (ALD) layer on the conductive region and the opening sidewalls; a second ALD layer on a portion of the first ALD layer, and a third ALD layer within the opening and on the first ALD layer. Other embodiments are described herein.

公开(公告)号：US20220415877A1

公开(公告)日：2022-12-29

申请号：US17358934

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Benjamin Orr ,  Rohit Grover ,  Nathan Jack ,  Nicholas Thomson ,  Rui Ma ,  Ayan Kar ,  Kalyan Kolluru

IPC: H01L27/02 ,  H01L27/088

Abstract: A semiconductor device includes a first interconnect and a second interconnect, a substrate between the first and second interconnects and one or more wells on the substrate on a first level. A second level includes a first fin and a second fin, each on the one or more wells, where the first fin and the one or more wells include dopants of a first conductivity type and the second fin includes a dopant of a second conductivity type. A third fin is over a first region between the substrate and the first interconnect, and a fourth fin is over a second region between the substrate and the second interconnect. A third interconnect is electrically coupled between the first interconnect and the first fin and a fourth interconnect is electrically coupled between the second interconnect and the second fin.

公开(公告)号：US09472456B2

公开(公告)日：2016-10-18

申请号：US14140085

申请日：2013-12-24

Applicant: Intel Corporation

Inventor： Erica J. Thompson ,  Nabil G. Mistkawi ,  Rohit Grover

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L21/321 ,  H01L21/3213

CPC classification number: H01L21/76897 ,  H01L21/32115 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76865

Abstract: Methods for selectively etching titanium and titanium nitride are disclosed. In some embodiments the method involve exposing a workpiece to a first solution to remove titanium nitride, exposing the workpiece to a second solution to remove titanium, and exposing the workpiece to a third solution to remove residual titanium nitride, if any. The solutions are formulated such that they may selectively remove titanium and/or titanium nitride, while not etching or not substantially etching certain other materials such as dielectric materials, oxides, and metals other than titanium.

Abstract translation: 公开了选择性蚀刻钛和氮化钛的方法。 在一些实施方案中，该方法包括将工件暴露于第一溶液以除去氮化钛，将工件暴露于第二溶液以除去钛，并将工件暴露于第三溶液以除去残留的氮化钛（如果有的话）。 这些溶液被配制成使得它们可以选择性地除去钛和/或氮化钛，同时不蚀刻或基本不蚀刻某些其他材料，例如电介质材料，氧化物和钛以外的金属。