公开(公告)号：US20220140076A1

公开(公告)日：2022-05-05

申请号：US17576765

申请日：2022-01-14

Applicant: Intel Corporation

Inventor： Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Nicholas MINUTILLO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20150325481A1

公开(公告)日：2015-11-12

申请号：US14798380

申请日：2015-07-13

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack KAVALIEROS ,  Willy RACHMADY ,  Van LE ,  Benjamin CHU-KUNG ,  Matthew METZ ,  Robert CHAU

IPC: H01L21/8258 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L21/306 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

Abstract translation: 在同一衬底（例如硅）上的非均质材料如III-V族半导体材料和IV族半导体（例如Ge）共同整合的体系结构和技术。 在实施例中，采用具有交替的纳米线和牺牲层的多层非均相半导体材料堆叠以释放纳米线并允许形成完全包围纳米线晶体管的沟道区域的同轴栅极结构。 在实施例中，各个PMOS和NMOS沟道半导体材料与具有交替的Ge / III-V层的覆盖层的起始衬底共同整合。 在实施例中，单个PMOS和单独NMOS器件内的多个堆叠的纳米线的垂直积分能够给出给定布局区域的显着的驱动电流。

公开(公告)号：US20190165106A1

公开(公告)日：2019-05-30

申请号：US16246356

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/15 ,  H01L27/088 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/20 ,  H01L29/06 ,  H01L29/04 ,  H01L23/66 ,  H01L29/78 ,  H01L29/205 ,  H01L27/06

CPC classification number: H01L29/158 ,  B82Y10/00 ,  H01L21/02603 ,  H01L23/66 ,  H01L27/0605 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/778 ,  H01L29/7786 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78681 ,  H01L29/78696 ,  H01L2223/6677 ,  Y10S977/938

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20170323972A1

公开(公告)日：2017-11-09

申请号：US15660574

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Robert S. CHAU ,  Suman DATTA ,  Jack KAVALIEROS ,  Justin K. BRASK ,  Mark L. DOCZY ,  Matthew METZ

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/267 ,  H01L29/207 ,  H01L29/45 ,  H01L29/51 ,  H01L29/16

CPC classification number: H01L29/201 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/20 ,  H01L29/207 ,  H01L29/267 ,  H01L29/41783 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7827 ,  H01L29/7836 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78681

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

公开(公告)号：US20170229354A1

公开(公告)日：2017-08-10

申请号：US15498280

申请日：2017-04-26

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack KAVALIEROS ,  Willy RACHMADY ,  Van LE ,  Benjamin CHU-KUNG ,  Matthew METZ ,  Robert CHAU

IPC: H01L21/84 ,  H01L29/423 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US20160343844A1

公开(公告)日：2016-11-24

申请号：US15229079

申请日：2016-08-04

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/04 ,  H01L29/10 ,  G06F1/16 ,  H03F3/195 ,  H01L29/66 ,  H01L21/02 ,  G06F1/18 ,  H01L29/20 ,  H03F3/213

CPC classification number: H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

Abstract: Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (1010) plane on a (110) plane of the silicon.

Abstract translation: 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性晶体半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区域。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，其中（1010）面在硅的（110）平面上。

公开(公告)号：US20200312978A1

公开(公告)日：2020-10-01

申请号：US16363952

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jack KAVALIEROS ,  Ian YOUNG ,  Matthew METZ ,  Uygar AVCI ,  Chia-Ching LIN ,  Owen LOH ,  Seung Hoon SUNG ,  Aditya KASUKURTI ,  Sou-Chi CHANG ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  G09G3/36 ,  G02F1/141 ,  H01L21/28

Abstract: Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

公开(公告)号：US20200006576A1

公开(公告)日：2020-01-02

申请号：US16024701

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Sean MA ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY

IPC: H01L29/786 ,  H01L29/205 ,  H01L29/423 ,  H01L29/04 ,  H01L29/66

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.

公开(公告)号：US20200006069A1

公开(公告)日：2020-01-02

申请号：US16024694

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/04 ,  H01L27/12 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.

公开(公告)号：US20190229022A1

公开(公告)日：2019-07-25

申请号：US16372272

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack KAVALIEROS ,  Willy RACHMADY ,  Van LE ,  Benjamin CHU-KUNG ,  Matthew METZ ,  Robert CHAU

IPC: H01L21/84 ,  H01L21/8258 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L29/20 ,  H01L29/16 ,  H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.