公开(公告)号：US20200066326A1

公开(公告)日：2020-02-27

申请号：US15776058

申请日：2015-12-23

申请人： Intel Corporation

发明人： Rafael RIOS ,  Gilbert DEWEY ,  Van H. LE ,  Jack KAVALIEROS ,  Mesut METERELLIYOZ

IPC分类号： G11C11/4097 ,  G11C11/405 ,  H01L27/108

摘要： A high retention time memory element is described that has dual gate devices. In one example, the memory element has a write transistor with a metal gate having a source coupled to a write bit line, a gate coupled to a write line, and a drain coupled to a storage node, wherein a value is written to the storage node by enabling the gate and applying the value to the bit line, and a read transistor having a source coupled to a read line, a gate coupled to the storage node, and a drain coupled to a read bit line, wherein the value of the storage node is sensed by applying a current to the source and reading the sense line to determine a status of the gate.

公开(公告)号：US20220140076A1

公开(公告)日：2022-05-05

申请号：US17576765

申请日：2022-01-14

申请人： Intel Corporation

发明人： Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Nicholas MINUTILLO

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

摘要： Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US20200287017A1

公开(公告)日：2020-09-10

申请号：US16294821

申请日：2019-03-06

申请人： Intel Corporation

发明人： Sou-Chi CHANG ,  Chia-Chang LIN ,  Seung Hoon SUNG ,  Ashish Verma PENUMATCHA ,  Nazila HARATIPOURA ,  Owen LOH ,  Jack KAVALIEROS ,  Uygar AVCI ,  Ian YOUNG

IPC分类号： H01L29/51 ,  H01L29/78 ,  H01L29/66

摘要： A gate stack is described that uses anti-ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2) or ferroelectric material (e.g., Si, La, N, Al, Zr, Ge, Y doped HfO2, perovskite ferroelectric such as NH4H2PO4, KH2PO4, LiNb03, LiTaO3, BaTiO3, PbTiO3, Pb (Zr,Ti) O3, (Pb,La)TiO3, and (Pb,La)(Zr,Ti)O3) which reduces write voltage, improves endurance, and increases retention. The gate stack of comprises strained anti-FE or FE material and depolarized anti-FE or FE. The endurance of the FE transistor is further improved by using a higher K (constant) dielectric (e.g., SiO2, Al2O3, HfO2, Ta2O3, La2O3) in the gate stack. High K effects may also be achieved by depolarizing the FE or FE oxide in the transistor gate stack.

公开(公告)号：US20150325481A1

公开(公告)日：2015-11-12

申请号：US14798380

申请日：2015-07-13

申请人： Intel Corporation

发明人： Marko RADOSAVLJEVIC ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Jack KAVALIEROS ,  Willy RACHMADY ,  Van LE ,  Benjamin CHU-KUNG ,  Matthew METZ ,  Robert CHAU

IPC分类号： H01L21/8258 ,  H01L21/8238 ,  H01L29/423 ,  H01L21/02 ,  H01L29/16 ,  H01L29/20 ,  H01L21/306 ,  H01L27/092 ,  H01L29/06

CPC分类号： H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

摘要翻译： 在同一衬底（例如硅）上的非均质材料如III-V族半导体材料和IV族半导体（例如Ge）共同整合的体系结构和技术。 在实施例中，采用具有交替的纳米线和牺牲层的多层非均相半导体材料堆叠以释放纳米线并允许形成完全包围纳米线晶体管的沟道区域的同轴栅极结构。 在实施例中，各个PMOS和NMOS沟道半导体材料与具有交替的Ge / III-V层的覆盖层的起始衬底共同整合。 在实施例中，单个PMOS和单独NMOS器件内的多个堆叠的纳米线的垂直积分能够给出给定布局区域的显着的驱动电流。

公开(公告)号：US20200006570A1

公开(公告)日：2020-01-02

申请号：US16024687

申请日：2018-06-29

申请人： Intel Corporation

发明人： Van H. LE ,  Rajat PAUL ,  Abhishek SHARMA ,  Tahir GHANI ,  Jack KAVALIEROS ,  Gilbert DEWEY ,  Matthew METZ ,  Miriam RESHOTKO ,  Benjamin CHU-KUNG ,  Justin WEBER ,  Shriram SHIVARAMAN

IPC分类号： H01L29/786 ,  H01L29/45

摘要： Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US20200006523A1

公开(公告)日：2020-01-02

申请号：US16024699

申请日：2018-06-29

申请人： Intel Corporation

发明人： Matthew METZ ,  Willy RACHMADY ,  Sean MA ,  Jessica TORRES ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Tahir GHANI

IPC分类号： H01L29/66 ,  H01L21/02

摘要： Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate with a surface that is substantially flat. A channel area including an III-V compound may be above the substrate, where the channel area is an epitaxial layer directly in contact with the surface of the substrate. A gate dielectric layer is adjacent to the channel area and in direct contact with the channel area, while a gate electrode is adjacent to the gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20190393356A1

公开(公告)日：2019-12-26

申请号：US16016381

申请日：2018-06-22

申请人： Intel Corporation

发明人： Van H. LE ,  Seung Hoon SUNG ,  Benjamin CHU-KUNG ,  Miriam RESHOTKO ,  Matthew METZ ,  Yih WANG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Tahir GHANI ,  Nazila HARATIPOUR ,  Abhishek SHARMA ,  Shriram SHIVARAMAN

IPC分类号： H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L27/108 ,  H01L23/522 ,  H01L29/66

摘要： Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20170263708A1

公开(公告)日：2017-09-14

申请号：US15605795

申请日：2017-05-25

申请人： Intel Corporation

发明人： Han Wui THEN ,  Robert CHAU ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack KAVALIEROS ,  Matthew METZ ,  Niloy MUKHERJEE ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC分类号： H01L29/06 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02 ,  H01L21/225 ,  H01L21/283 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/324 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/20

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  G05F3/02 ,  H01L21/02603 ,  H01L21/02636 ,  H01L21/225 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/32133 ,  H01L21/324 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/78696

摘要： Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US20200312978A1

公开(公告)日：2020-10-01

申请号：US16363952

申请日：2019-03-25

申请人： Intel Corporation

发明人： Jack KAVALIEROS ,  Ian YOUNG ,  Matthew METZ ,  Uygar AVCI ,  Chia-Ching LIN ,  Owen LOH ,  Seung Hoon SUNG ,  Aditya KASUKURTI ,  Sou-Chi CHANG ,  Tanay GOSAVI ,  Ashish Verma PENUMATCHA

IPC分类号： H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  G09G3/36 ,  G02F1/141 ,  H01L21/28

摘要： Techniques and mechanisms for providing electrical insulation or other protection of an integrated circuit (IC) device with a spacer structure which comprises an (anti)ferromagnetic material. In an embodiment, a transistor comprises doped source or drain regions and a channel region which are each disposed in a fin structure, wherein a gate electrode and an underlying dielectric layer of the transistor each extend over the channel region. Insulation spacers are disposed on opposite sides of the gate electrode, where at least a portion of one such insulation spacer comprises an (anti)ferroelectric material. Another portion of the insulation spacer comprises a non-(anti)ferroelectric material. In another embodiment, the two portions of the spacer are offset vertically from one another, wherein the (anti)ferroelectric portion forms a bottom of the spacer.

公开(公告)号：US20200006576A1

公开(公告)日：2020-01-02

申请号：US16024701

申请日：2018-06-29

申请人： Intel Corporation

发明人： Sean MA ,  Nicholas MINUTILLO ,  Cheng-Ying HUANG ,  Tahir GHANI ,  Jack KAVALIEROS ,  Anand MURTHY ,  Harold KENNEL ,  Gilbert DEWEY ,  Matthew METZ ,  Willy RACHMADY

IPC分类号： H01L29/786 ,  H01L29/205 ,  H01L29/423 ,  H01L29/04 ,  H01L29/66

摘要： Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.