公开(公告)号：US20200098874A1

公开(公告)日：2020-03-26

申请号：US16141301

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Justin WEBER ,  Harold KENNEL ,  Abhishek SHARMA ,  Christopher JEZEWSKI ,  Matthew V. METZ ,  Tahir GHANI ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Van H. LE ,  Arnab SEN GUPTA

IPC: H01L29/36 ,  H01L29/22 ,  H01L29/24 ,  H01L29/47 ,  H01L29/267 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L21/322

Abstract: Embodiments herein describe techniques for an integrated circuit that includes a substrate, a semiconductor device on the substrate, and a contact stack above the substrate and coupled to the semiconductor device. The contact stack includes a contact metal layer, and a semiconducting oxide layer adjacent to the contact metal layer. The semiconducting oxide layer includes a semiconducting oxide material, while the contact metal layer includes a metal with a sufficient Schottky-barrier height to induce an interfacial electric field between the semiconducting oxide layer and the contact metal layer to reject interstitial hydrogen from entering the semiconductor device through the contact stack. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199839A1

公开(公告)日：2022-06-23

申请号：US17133599

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Arnab SEN GUPTA ,  Urusa ALAAN ,  Justin WEBER ,  Charles C. KUO ,  Yu-Jin CHEN ,  Kaan OGUZ ,  Matthew V. METZ ,  Abhishek A. SHARMA ,  Prashant MAJHI ,  Brian S. DOYLE ,  Van H. LE

IPC: H01L29/872 ,  H01L27/07 ,  H01L29/47 ,  H01L29/22

Abstract: Embodiments disclosed herein include semiconductor devices with Schottky diodes in a back end of line stack. In an embodiment, a semiconductor device comprises a semiconductor layer, where transistor devices are provided in the semiconductor layer, and a back end stack over the semiconductor layer. In an embodiment, a diode is in the back end stack. In an embodiment, the diode comprises a first electrode, a semiconductor region over the first electrode, and a second electrode over the semiconductor region. In an embodiment, a first interface between the first electrode and the semiconductor region is an ohmic contact, and a second interface between the semiconductor region and the second electrode is a Schottky contact.

公开(公告)号：US20190393249A1

公开(公告)日：2019-12-26

申请号：US16016387

申请日：2018-06-22

Applicant: Intel Corporation

Inventor： Aaron LILAK ,  Justin WEBER ,  Harold KENNEL ,  Willy RACHMADY ,  Gilbert DEWEY ,  Van H. LE ,  Abhishek SHARMA ,  Patrick MORROW

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/78 ,  H01L21/8256

Abstract: Embodiments herein describe techniques for a semiconductor device including a first transistor above a substrate, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor includes a first channel layer above the substrate, and a first gate electrode above the first channel layer. The insulator layer is next to a first source electrode of the first transistor above the first channel layer, next to a first drain electrode of the first transistor above the first channel layer, and above the first gate electrode. The second transistor includes a second channel layer above the insulator layer, and a second gate electrode separated from the second channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20240186398A1

公开(公告)日：2024-06-06

申请号：US18073213

申请日：2022-12-01

Applicant: Intel Corporation

Inventor： Aaron D. LILAK ,  Anh PHAN ,  Rishabh MEHANDRU ,  Stephen M. CEA ,  Patrick MORROW ,  Jack T. KAVALIEROS ,  Justin WEBER ,  Salim BERRADA

IPC: H01L29/49 ,  H01L21/28 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/4991 ,  H01L21/28123 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/516 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

Abstract: Integrated circuit structures having cavity spacers, and methods of fabricating integrated circuit structures having cavity spacers, are described. For example, an integrated circuit structure includes a sub-fin structure over a stack of nanowires. A gate structure is vertically around the stack of nanowires. An internal gate spacer is between vertically adjacent ones of the nanowires and adjacent to the gate structure. A trench contact structure is laterally adjacent to a side of the gate structure. A cavity spacer is laterally between the gate structure and the trench contact structure.

公开(公告)号：US20200006570A1

公开(公告)日：2020-01-02

申请号：US16024687

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Van H. LE ,  Rajat PAUL ,  Abhishek SHARMA ,  Tahir GHANI ,  Jack KAVALIEROS ,  Gilbert DEWEY ,  Matthew METZ ,  Miriam RESHOTKO ,  Benjamin CHU-KUNG ,  Justin WEBER ,  Shriram SHIVARAMAN

IPC: H01L29/786 ,  H01L29/45

Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.