FERROELECTRIC FIELD-EFFECT TRANSISTOR DEVICES HAVING A TOP GATE AND A BOTTOM GATE

    公开(公告)号:US20210175238A1

    公开(公告)日:2021-06-10

    申请号:US17155015

    申请日:2021-01-21

    申请人: Intel Corporation

    摘要: Techniques are disclosed for forming integrated circuit (IC) devices that include ferroelectric field-effect transistors (FE-FETs) having a top gate and a bottom gate (or, generally, a dual-gate configuration). The disclosed FE-FET devices may be formed in the back end of the IC structure and may be implemented with various materials that exhibit ferroelectric properties when processed at temperatures within the thermal budget of the back-end processing. The disclosed back-end FE-FET devices can achieve greater than two resistance states, depending on the direction of poling of the top and bottom gates, thereby enabling the formation of 3-state and 4-state memory devices, for example. Additionally, as will be appreciated in light of this disclosure, the disclosed back-end FE-FET devices can free up floor space in the front-end, thereby providing space for additional devices in the front-end.

    CAPACITOR WITH DUAL DIELECTRIC LAYERS

    公开(公告)号:US20230087624A1

    公开(公告)日:2023-03-23

    申请号:US17483795

    申请日:2021-09-23

    申请人: Intel Corporation

    IPC分类号: H01L49/02

    摘要: Embodiments described herein may be related to apparatuses, processes, and techniques related to increasing the capacitance density of MIM capacitors on dies or within packages. In particular, a MIM stack is disclosed that has multiple insulator layers between the metal, in order to increase the dielectric constant of the MIM stack. In particular, the first dielectric layer may include strontium, titanium, and oxygen and may be physically coupled with a second dielectric layer that may include barium, strontium, titanium, and oxygen. Other embodiments may be described and/or claimed.