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    4F2 DRAM CELL USING VERTICAL THIN FILM TRANSISTOR
    2.
    发明申请
    4F2 DRAM CELL USING VERTICAL THIN FILM TRANSISTOR 审中-公开

    公开(公告)号：US20190393222A1

    公开(公告)日：2019-12-26

    申请号：US16013798

    申请日：2018-06-20

    申请人： Intel Corporation

    发明人： Abhishek SHARMA ,  Yih WANG

    IPC分类号： H01L27/108 ,  H01L29/786

    摘要： Embodiments include a transistor device that comprises a gate electrode and a gate dielectric surrounding the gate electrode. In an embodiment, a source region may be below the gate electrode and a drain region may be above the gate electrode. In an embodiment, a channel region may be between the source region and the drain region. In an embodiment, the channel region is separated from a sidewall of the gate electrode by the gate dielectric. In an embodiment, a capacitor may be electrically coupled to the drain region.

    LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS
    4.
    发明申请
    LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS 审中-公开

    公开(公告)号：US20180277593A1

    公开(公告)日：2018-09-27

    申请号：US15959027

    申请日：2018-04-20

    申请人： Intel Corporation

    发明人： Kevin J. LEE ,  Tahir GHANI ,  Joseph M. STEIGERWALD ,  John H. EPPLE ,  Yih WANG

    IPC分类号： H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

    CPC分类号： H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12 ,  H05K999/99

    摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

    APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY
    5.
    发明申请
    APPARATUS FOR LOW POWER WRITE AND READ OPERATIONS FOR RESISTIVE MEMORY 审中-公开

    公开(公告)号：US20200020378A1

    公开(公告)日：2020-01-16

    申请号：US16565299

    申请日：2019-09-09

    申请人： Intel Corporation

    发明人： Liqiong WEI ,  Fatih HAMZAOGLU ,  Yih WANG ,  Nathaniel J. AUGUST ,  Blake C. LIN ,  Cyrille DRAY

    IPC分类号： G11C11/16 ,  G11C13/00 ,  G11C29/02

    摘要： Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

    DAMASCENE-BASED APPROACHES FOR EMBEDDING SPIN HALL MTJ DEVICES INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES
    6.
    发明申请
    DAMASCENE-BASED APPROACHES FOR EMBEDDING SPIN HALL MTJ DEVICES INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES 审中-公开

    公开(公告)号：US20190013354A1

    公开(公告)日：2019-01-10

    申请号：US16067803

    申请日：2016-03-18

    申请人： Intel Corporation

    发明人： Kevin J. LEE ,  Yih WANG

    IPC分类号： H01L27/22 ,  H01L43/04 ,  H01L23/528 ,  H01L43/14 ,  H01L21/8234 ,  H01F41/34 ,  H01F10/32

    摘要： Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.

    6F2 NON-VOLATILE MEMORY BITCELL
    7.
    发明申请
    6F2 NON-VOLATILE MEMORY BITCELL 有权
    6F2非易失性存储器BITCELL

    公开(公告)号：US20170069826A1

    公开(公告)日：2017-03-09

    申请号：US15122093

    申请日：2014-03-28

    申请人： Intel Corporation

    发明人： Yih WANG

    IPC分类号： H01L43/02 ,  G03F1/36 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08

    CPC分类号： H01L43/02 ,  G03F1/36 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    摘要： An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

    摘要翻译： 一种装置，包括以相对于彼此大体上正交取向的字线和位线限定的格栅布置的存储单元阵列，包括电阻存储器组件和存取晶体管的存储单元，其中所述存取晶体管包括扩散区 相对于相关联的字线以锐角设置。 一种方法，包括蚀刻衬底以形成多个鳍片，每个鳍片包括具有包括多个第一接合区域的多个第一接合区域和多个第二接合区域的主体，所述多个第一接合区域和多个第二接合区域彼此大致平行并且通过位于 长度尺寸是从第二连接区域的开始的第一结区域的端部; 去除间隔物材料; 以及在所述多个翅片中的每一个的所述沟道区上引入栅电极。

    MEMORY CELL WITH IMPROVED WRITE MARGIN
    8.
    发明申请
    MEMORY CELL WITH IMPROVED WRITE MARGIN 审中-公开
    具有改进的写字符的存储单元

    公开(公告)号：US20150235696A1

    公开(公告)日：2015-08-20

    申请号：US14703723

    申请日：2015-05-04

    申请人： Intel Corporation

    发明人： Yih WANG ,  Muhammad M. KHELLAH ,  Fatih HAMZAOGLU

    IPC分类号： G11C11/419

    CPC分类号： G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

    摘要： Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

    摘要翻译： 描述了一种用于改善存储器单元中的写入裕度的装置和系统。 在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段 的脉冲信号。 在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。