公开(公告)号：US20150235696A1

公开(公告)日：2015-08-20

申请号：US14703723

申请日：2015-05-04

Applicant: Intel Corporation

Inventor： Yih WANG ,  Muhammad M. KHELLAH ,  Fatih HAMZAOGLU

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

Abstract translation: 描述了一种用于改善存储器单元中的写入裕度的装置和系统。 在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段 的脉冲信号。 在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。

公开(公告)号：US20230284427A1

公开(公告)日：2023-09-07

申请号：US17686241

申请日：2022-03-03

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Seenivasan SUBRAMANIAM ,  Patrick MORROW ,  Muhammad M. KHELLAH

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C11/412 ,  G11C11/419

Abstract: Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and/or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying M0 metal layer and an underlying BM0 metal layers to reduce capacitance.

公开(公告)号：US20200258890A1

公开(公告)日：2020-08-13

申请号：US16859600

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Somnath PAUL ,  Muhammad M. KHELLAH ,  Chen KOREN

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: An ultra-deep compute Static Random Access Memory (SRAM) with high compute throughput and multi-directional data transfer capability is provided. Compute units are placed in both horizontal and vertical directions to achieve a symmetric layout while enabling communication between the compute units. An SRAM array supports simultaneous read and write to the left and right section of the same SRAM subarray by duplicating pre-decoding logic inside the SRAM array. This allows applications with non-overlapping read and write address spaces to have twice the bandwidth as compared to a baseline SRAM array.

公开(公告)号：US20170229166A1

公开(公告)日：2017-08-10

申请号：US15496655

申请日：2017-04-25

Applicant: Intel Corporation

Inventor： Yih WANG ,  Muhammad M. KHELLAH ,  Fatih HAMZAOGLU

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

公开(公告)号：US20200183922A1

公开(公告)日：2020-06-11

申请号：US16795516

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Wootaek LIM ,  Minchang CHO ,  Somnath PAUL ,  Charles AUGUSTINE ,  Suyoung BANG ,  Turbo MAJUMDER ,  Muhammad M. KHELLAH

IPC: G06F16/2453 ,  G06F7/08 ,  G06F7/20 ,  G11C15/04

Abstract: An apparatus is described. The apparatus includes a nearest neighbor search circuit to perform a search according to a first stage search and a second stage search. The nearest neighbor search circuit includes a first stage circuit and a second stage circuit. The first stage search circuit includes a hash logic circuit and a content addressable memory. The hash logic circuit is to generate a hash word from a input query vector. The hash word has B bands. The content addressable memory is to store hashes of a random access memory's data items. The hashes each have B bands. The content addressable memory is to compare the hashes against the hash word on a sequential band-by-band basis. The second stage circuit char the random access memory and a compare and sort circuit. The compare and sort circuit is to receive the input query vector. The random access memory has crosswise bit lines coupled to the compare and sort circuit. The compare and sort circuit is to identify k nearest ones of the data items whose hashes were selected by the content addressable memory.

公开(公告)号：US20190043583A1

公开(公告)日：2019-02-07

申请号：US16110990

申请日：2018-08-23

Applicant: INTEL CORPORATION

Inventor： Turbo MAJUMDER ,  Somnath PAUL ,  Charles AUGUSTINE ,  Muhammad M. KHELLAH

IPC: G11C15/04 ,  G11C8/10 ,  G06F17/30 ,  G06T1/60

Abstract: Provided are an apparatus, video processing unit, and method for clustering events in a content addressable memory. An event is received including at least one parameter value and a timestamp. A determination is made as to whether there is a valid entry in the memory having at least one parameter value within a predefined range of values of the at least one parameter value in the event. In response to a determination that there is the valid entry, writing the at least one parameter value and the timestamp in the event to the valid entry.

公开(公告)号：US20180024761A1

公开(公告)日：2018-01-25

申请号：US15706521

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： Pascal A. MEINERZHAGEN ,  Stephen T. KIM ,  Anupama A. THAPLOO ,  Muhammad M. KHELLAH

IPC: G06F3/06 ,  G11C5/14

CPC classification number: G11C5/148

Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.