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1.发明申请公开(公告)号：US20190165128A1
公开(公告)日：2019-05-30
申请号：US16100317
申请日：2018-08-10
发明人： SEYOUNG KIM , CHOONGHYUN LEE , INJO OK , SOON-CHEON SEO
IPC分类号： H01L29/66 , H01L21/02 , H01L29/10 , H01L29/737 , H01L29/732 , H01L21/324 , H01L21/308 , H01L21/306 , H01L29/165
CPC分类号： H01L29/66242 , H01L21/02112 , H01L21/0228 , H01L21/02532 , H01L21/30604 , H01L21/308 , H01L21/324 , H01L29/0684 , H01L29/0817 , H01L29/1004 , H01L29/165 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L29/737 , H01L29/7371 , H01L29/7378 , H01L2924/1305
摘要： A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a silicon germanium layer are performed to form a plurality of vertical fins each including a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on a first semiconductor layer above a substrate. First spacers are formed on sidewalls of the plurality of vertical fins. Exposed silicon germanium layer above the first semiconductor layer is directionally etched away. A germanium oxide layer is conformally coated to cover all exposed top and sidewall surfaces. Condensation annealing followed by silicon oxide strip is performed. The first spacers, remaining germanium oxide layer and the hard mask pattern are removed. A dielectric material is deposited to isolate the plurality of vertical fins. An emitter, a base and a collector contacts are formed to connect to the second semiconductor pattern, the silicon germanium pattern and the first semiconductor layer, respectively. The BJT structures manufactured are also provided.
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公开(公告)号：US20180323288A1
公开(公告)日：2018-11-08
申请号：US16030359
申请日：2018-07-09
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/165 , H01L29/161 , H01L29/16 , H01L29/10 , H01L29/08
CPC分类号： H01L29/66795 , H01L29/0638 , H01L29/0649 , H01L29/0847 , H01L29/1083 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/7848 , H01L29/785
摘要： A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
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公开(公告)号：US20170154982A1
公开(公告)日：2017-06-01
申请号：US15432320
申请日：2017-02-14
CPC分类号： H01L29/66795 , H01L29/0638 , H01L29/0649 , H01L29/0847 , H01L29/1083 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/7848 , H01L29/785
摘要： A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
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公开(公告)号：US20230263077A1
公开(公告)日：2023-08-17
申请号：US18164125
申请日：2023-02-03
发明人： TAKASHI ANDO , HIROYUKI MIYAZOE , EDUARD ALBERT CARTIER , BABAR KHAN , YOUNGSEOK KIM , DEXIN KONG , SOON-CHEON SEO , JOEL P. DE SOUZA
CPC分类号： H10N70/041 , H10B63/80 , H10N70/021 , H10N70/826 , H10N70/841 , H10N70/8833
摘要： Embodiments of the invention provide a resistive switching device that includes a metal interconnect electrode and a memory stack over the metal interconnect electrode. The memory stack includes a plurality of layers that includes a top electrode, a plasma-treated bottom electrode, and a dielectric layer between the top electrode and the plasma-treated bottom electrode. The plasma-treated bottom electrode includes a portion of a blanket bottom electrode layer. The plasma-treated bottom electrode further includes a current-conducting filament characteristic that results from a charge particle treatment applied to the blanket bottom electrode while a top surface of the blanket bottom electrode is exposed.
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公开(公告)号：US20210391536A1
公开(公告)日：2021-12-16
申请号：US16898527
申请日：2020-06-11
发明人： TAKASHI ANDO , HIROYUKI MIYAZOE , EDUARD ALBERT CARTIER , BABAR KHAN , YOUNGSEOK KIM , DEXIN KONG , SOON-CHEON SEO , JOEL P. DE SOUZA
摘要： Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.
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公开(公告)号：US20190259939A1
公开(公告)日：2019-08-22
申请号：US15899933
申请日：2018-02-20
发明人： SOON-CHEON SEO , Kisup Chung , Injo OK , Seyoung Kim , Choonghyun Lee
摘要： Methods for MTJ patterning for a MTJ device are provided. For example, a method includes (a) providing an MTJ device comprising a substrate comprising a plurality of bottom electrodes, a MTJ layer disposed on the substrate, and a plurality of pillars disposed on the MTJ layer and over the plurality of bottom electrodes, wherein the plurality of pillars comprise a metal layer and a hard mask layer disposed on the metal layer, (b) conducting a first ion beam etching of the MTJ device; (c) rotating the MTJ device by 90 degrees in a clockwise or a counter clockwise direction about an axis perpendicular to a top surface of the MTJ device from a starting position; (d) conducting a second ion beam etching of the MTJ device; and (e) repeating steps (c) and (d).
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公开(公告)号：US20160172498A1
公开(公告)日：2016-06-16
申请号：US15049796
申请日：2016-02-22
IPC分类号： H01L29/78 , H01L29/08 , H01L29/06 , H01L29/16 , H01L29/165 , H01L29/66 , H01L29/161
CPC分类号： H01L29/66795 , H01L29/0638 , H01L29/0649 , H01L29/0847 , H01L29/1083 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/7848 , H01L29/785
摘要： A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
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