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公开(公告)号:US20180323202A1
公开(公告)日:2018-11-08
申请号:US15585826
申请日:2017-05-03
IPC分类号: H01L27/112 , H01L23/525 , H01L23/00
CPC分类号: H01L27/11206 , H01L23/5256 , H01L23/573
摘要: A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses.
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公开(公告)号:US20160172498A1
公开(公告)日:2016-06-16
申请号:US15049796
申请日:2016-02-22
IPC分类号: H01L29/78 , H01L29/08 , H01L29/06 , H01L29/16 , H01L29/165 , H01L29/66 , H01L29/161
CPC分类号: H01L29/66795 , H01L29/0638 , H01L29/0649 , H01L29/0847 , H01L29/1083 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/7848 , H01L29/785
摘要: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
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公开(公告)号:US20180323203A1
公开(公告)日:2018-11-08
申请号:US16012951
申请日:2018-06-20
IPC分类号: H01L27/112 , H01L23/00 , H01L23/525
摘要: A method for forming a semiconductor device includes forming a nanosheet stack comprising alternating layers of a first material and a second material on a substrate. The method further includes removing portions of the stack to form tapered stack sidewalls, which have a taper angle in relation to a horizontal surface of the substrate. The method further includes converting the second material to a resistive material. The layers that include the resistive material form one or more electrical fuses.
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公开(公告)号:US20180323288A1
公开(公告)日:2018-11-08
申请号:US16030359
申请日:2018-07-09
IPC分类号: H01L29/66 , H01L29/78 , H01L29/06 , H01L29/165 , H01L29/161 , H01L29/16 , H01L29/10 , H01L29/08
CPC分类号: H01L29/66795 , H01L29/0638 , H01L29/0649 , H01L29/0847 , H01L29/1083 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/7848 , H01L29/785
摘要: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
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公开(公告)号:US20170154982A1
公开(公告)日:2017-06-01
申请号:US15432320
申请日:2017-02-14
CPC分类号: H01L29/66795 , H01L29/0638 , H01L29/0649 , H01L29/0847 , H01L29/1083 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/66553 , H01L29/66636 , H01L29/7848 , H01L29/785
摘要: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.
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