公开(公告)号：US10475904B2

公开(公告)日：2019-11-12

申请号：US15868004

申请日：2018-01-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Hiroaki Niimi ,  Steven Bentley ,  Romain Lallement ,  Brent A. Anderson ,  Junli Wang ,  Muthumanickam Sankarapandian

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/11 ,  H01L21/8238

摘要： A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region.

公开(公告)号：US20190214484A1

公开(公告)日：2019-07-11

申请号：US15868004

申请日：2018-01-11

申请人： GLOBALFOUNDRIES Inc.

发明人： Hiroaki Niimi ,  Steven Bentley ,  Romain Lallement ,  Brent A. Anderson ,  Junli Wang ,  Muthumanickam Sankarapandian

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/092

摘要： A method of forming a merged source/drain region is disclosed that includes forming first and second VOCS structures above a semiconductor substrate, forming a recess in the substrate between the first and second VOCS structures and forming a P-type-doped semiconductor material in the recess. In this particular example, the method also includes removing a first substantially horizontally-oriented portion of the P-type-doped semiconductor material from within the recess while leaving a second substantially horizontally-oriented portion of the P-type-doped semiconductor material remaining in the recess and forming a substantially horizontally-oriented N-type-doped semiconductor material in the recess laterally adjacent the second substantially horizontally-oriented portion of the P-type-doped semiconductor material, wherein the substantially horizontally-oriented N-type-doped semiconductor material physically engages the second substantially horizontally-oriented portion of the P-type-doped semiconductor material along an interface within the merged source/drain region.

公开(公告)号：US10256235B2

公开(公告)日：2019-04-09

申请号：US15893860

申请日：2018-02-12

申请人： GLOBALFOUNDRIES INC.

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10

摘要： One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.

公开(公告)号：US09887192B2

公开(公告)日：2018-02-06

申请号：US15198044

申请日：2016-06-30

申请人： GLOBALFOUNDRIES Inc.

发明人： Edward J. Nowak ,  Brent A. Anderson

IPC分类号： H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/08 ,  H01L21/8234

CPC分类号： H01L27/088 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/66666 ,  H01L29/7827

摘要： Structures and fabrication methods for vertical-transport field-effect transistors. The structure includes a vertical-transport field-effect transistor having a source/drain region located in a semiconductor layer, a fin projecting from the source/drain region in the semiconductor layer, and a gate electrode on the semiconductor layer and coupled with the fin. The structure further includes an interconnect located in a trench defined in the semiconductor layer. The interconnect is coupled with the source/drain region or the gate electrode of the vertical-transport field-effect transistor, and may be used to couple the source/drain region or the gate electrode of the vertical-transport field-effect transistor with a source/drain region or a gate electrode of another vertical-transport field-effect transistor.

公开(公告)号：US20170294385A1

公开(公告)日：2017-10-12

申请号：US15634135

申请日：2017-06-27

申请人： GlobalFoundries Inc.

发明人： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC分类号： H01L23/528 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851

摘要： Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

公开(公告)号：US09443857B2

公开(公告)日：2016-09-13

申请号：US14561999

申请日：2014-12-05

申请人： GlobalFoundries Inc.

发明人： Brent A. Anderson ,  John E. Barth, Jr. ,  Edward J. Nowak

IPC分类号： H01L27/108 ,  H01L29/00 ,  H01L31/036 ,  H01L31/112 ,  H01L27/12 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768

CPC分类号： H01L27/10829 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76877 ,  H01L21/84 ,  H01L27/10826 ,  H01L27/10832 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/10885 ,  H01L27/1203

摘要： Systems and methods of forming semiconductor devices. A trench capacitor comprising deep trenches is formed in an n+ type substrate. The deep trenches have a lower portion partially filled with a trench conductor surrounded by a storage dielectric. A polysilicon growth is formed in an upper portion of the deep trenches. The semiconductor device includes a single-crystal semiconductor having an angled seam separating a portion of the polysilicon growth from an exposed edge of the deep trenches. A word-line is wrapped around the single-crystal semiconductor. A bit-line overlays the single-crystal semiconductor.

摘要翻译： 形成半导体器件的系统和方法。 包括深沟槽的沟槽电容器形成在n +型衬底中。 深沟槽具有部分地填充有由存储电介质包围的沟槽导体的下部。 在深沟槽的上部形成多晶硅生长。 半导体器件包括单晶半导体，其具有将多晶硅生长的一部分与深沟槽的暴露边缘分开的成角度的接缝。 字线缠绕在单晶半导体上。 位线覆盖单晶半导体。

公开(公告)号：US10020224B2

公开(公告)日：2018-07-10

申请号：US14980320

申请日：2015-12-28

申请人： GLOBALFOUNDRIES INC.

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L21/76835 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76819 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295

摘要： A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a hard mask adjacent to the conductive line after the conductive line forming; forming a second dielectric layer over the hard mask; and forming a via opening to the conductive line in the second dielectric layer. The via opening lands at least partially on the hard mask to self-align the via opening to the conductive line. A via may be formed by filling the via opening with a conductor.

公开(公告)号：US09935106B2

公开(公告)日：2018-04-03

申请号：US15088874

申请日：2016-04-01

申请人： GLOBALFOUNDRIES INC.

发明人： Edward J. Nowak ,  Brent A. Anderson ,  Robert R. Robison

IPC分类号： H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L21/8238 ,  H01L21/84

CPC分类号： H01L27/092 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/045

摘要： The present disclosure generally relates to semiconductor structures and, more particularly, to multi-finger devices in multiple-gate-contacted-pitch, integrated structures and methods of manufacture. The structure includes: a first plurality of fin structures formed on a substrate having a channel surface in a {110} plane; and a second plurality of fin structures formed on the substrate with a channel surface in a {100} plane, positioned in relation to the first plurality of fin structures.

公开(公告)号：US20180012988A1

公开(公告)日：2018-01-11

申请号：US15678206

申请日：2017-08-16

申请人： GLOBALFOUNDRIES INC.

发明人： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3115 ,  H01L21/762

CPC分类号： H01L29/785 ,  H01L21/31155 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

摘要： A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

公开(公告)号：US20180006024A1

公开(公告)日：2018-01-04

申请号：US15198309

申请日：2016-06-30

申请人： GLOBALFOUNDRIES INC.

发明人： Brent A. Anderson ,  Edward J. Nowak

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/088 ,  H01L21/823468 ,  H01L21/823487

摘要： One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.