公开(公告)号：US09263517B2

公开(公告)日：2016-02-16

申请号：US13835463

申请日：2013-03-15

申请人： GLOBALFOUNDRIES INC.

发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Jason E. Cummings ,  Toshiharu Furukawa ,  Robert J. Gauthier ,  Jed H. Rankin ,  Robert R. Robison ,  William R. Tonti

IPC分类号： H01L21/70 ,  H01L29/06 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L29/0649 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/1203

摘要： Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.

摘要翻译： 各种方面包括极薄的绝缘体上半导体（ETSOI）层。 在一个实施例中，ETSOI层包括限定多个不同的绝缘体上半导体（SOI）区域的多个浅沟槽隔离（STI），不同的SOI区域具有至少三个不同的厚度; 位于不同SOI区域内的至少一个凹部; 和在所述至少一个凹部上的氧化物盖。

公开(公告)号：US09847416B1

公开(公告)日：2017-12-19

申请号：US15351597

申请日：2016-11-15

申请人： GLOBALFOUNDRIES INC.

发明人： Edward J. Nowak ,  Robert R. Robison ,  Brent A. Anderson

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/04 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/7843 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/78696

摘要： Disclosed are performance-enhanced vertical devices (e.g., vertical field effect transistors (FETs) or complementary metal oxide semiconductor (CMOS) devices, which incorporate vertical FETs) and methods of forming such devices. A strained dielectric layer is positioned laterally adjacent to the gate of a vertical FET, increasing the charge carrier mobility within the channel region and improving performance. In a vertical n-type FET (NFET), the strain is compressive to improve electron mobility given the direction of current within the vertical NFET; whereas, in a vertical p-type FET (PFET), the strain is tensile to improve hole mobility given the direction of current within the vertical PFET. Optionally, the orientation of a vertical FET relative to the surface plane of the semiconductor wafer on which it is formed is also preplanned as function of the type of FET (i.e., NFET or PFET) for optimal charge carrier mobility and, thereby enhanced performance.

公开(公告)号：US09536882B2

公开(公告)日：2017-01-03

申请号：US14574504

申请日：2014-12-18

申请人： GLOBALFOUNDRIES INC.

发明人： Brent A. Anderson ,  Edward J. Nowak ,  Robert R. Robison ,  Andreas Scholze

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/3213 ,  H01L21/321 ,  H01L29/10

CPC分类号： H01L27/0924 ,  H01L21/32115 ,  H01L21/32133 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/1087

摘要： Disclosed are isolation techniques for bulk FinFETs. A semiconductor device includes a semiconductor substrate with a fin structure on the semiconductor substrate. The fin structure is perpendicular to the semiconductor substrate and has an upper portion and a lower portion. Source and drain regions are adjacent to the fin structure. A gate structure surrounds the upper portion of the fin structure. A well contact point is provided in the semiconductor substrate. The lower portion of the fin structure includes a sub-fin between the region surrounded by the gate structure and the semiconductor substrate. The sub-fin directly contacts the semiconductor substrate. The upper portion of the fin structure and an upper portion of the sub-fin are undoped. A lower portion of the sub-fin may be doped. Electrical potential applied from the well contact point to the lower portion of the sub-fin reduces leakage currents from the upper portion of the fin structure.

摘要翻译： 公开了用于散装FinFET的隔离技术。 半导体器件包括在半导体衬底上具有翅片结构的半导体衬底。 翅片结构垂直于半导体衬底并具有上部和下部。 源极和漏极区域与翅片结构相邻。 栅极结构围绕鳍结构的上部。 在半导体衬底中提供良好的接触点。 翅片结构的下部包括在被栅极结构包围的区域和半导体衬底之间的子鳍。 子鳍直接接触半导体衬底。 翅片结构的上部和副翅片的上部是未掺杂的。 子鳍片的下部可以被掺杂。 从阱接触点施加到副散热片的下部的电势减小了从翅片结构的上部的泄漏电流。

公开(公告)号：US09240406B2

公开(公告)日：2016-01-19

申请号：US14257143

申请日：2014-04-21

申请人： GLOBALFOUNDRIES INC.

发明人： Kai D. Feng ,  Dan Moy ,  Chengwen Pei ,  Robert R. Robison ,  Pinping Sun ,  Richard A. Wachnik ,  Ping-Chuan Wang

IPC分类号： H01L27/07 ,  H01L29/66 ,  H01L29/94

CPC分类号： H01L27/0733 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/11206 ,  H01L29/66181 ,  H01L29/945

摘要： A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

摘要翻译： 电容器结构可以包括多个沟槽电容器的并联连接。 电连接多个沟槽电容器的第一节点以提供电容器结构的第一节点。 多个沟槽电容器的第二节点通过电容器结构的第二节点处的至少一个可编程电连接电连接在一起。 每个可编程电气连接可以包括可编程电熔丝和场效应晶体管中的至少一个，并且可以临时或永久地断开相应的沟槽电容器。 可以通过暂时或永久地编程至少一个可编程电连接来调节电容器结构的总电容。

公开(公告)号：US09935106B2

公开(公告)日：2018-04-03

申请号：US15088874

申请日：2016-04-01

申请人： GLOBALFOUNDRIES INC.

发明人： Edward J. Nowak ,  Brent A. Anderson ,  Robert R. Robison

IPC分类号： H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L21/8238 ,  H01L21/84

CPC分类号： H01L27/092 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/045

摘要： The present disclosure generally relates to semiconductor structures and, more particularly, to multi-finger devices in multiple-gate-contacted-pitch, integrated structures and methods of manufacture. The structure includes: a first plurality of fin structures formed on a substrate having a channel surface in a {110} plane; and a second plurality of fin structures formed on the substrate with a channel surface in a {100} plane, positioned in relation to the first plurality of fin structures.

公开(公告)号：US20170287911A1

公开(公告)日：2017-10-05

申请号：US15088874

申请日：2016-04-01

申请人： GLOBALFOUNDRIES INC.

发明人： Edward J. Nowak ,  Brent A. Anderson ,  Robert R. Robison

IPC分类号： H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04

CPC分类号： H01L27/092 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/045

摘要： The present disclosure generally relates to semiconductor structures and, more particularly, to multi-finger devices in multiple-gate-contacted-pitch, integrated structures and methods of manufacture. The structure includes: a first plurality of fin structures formed on a substrate having a channel surface in a {110} plane; and a second plurality of fin structures formed on the substrate with a channel surface in a {100} plane, positioned in relation to the first plurality of fin structures.

公开(公告)号：US20170062609A1

公开(公告)日：2017-03-02

申请号：US15351753

申请日：2016-11-15

申请人： GLOBALFOUNDRIES INC.

发明人： Lyndon R. Logan ,  Edward J. Nowak ,  Robert R. Robison

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L29/7816 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7835 ,  H01L29/785

摘要： Devices and methods for a high voltage FinFET with a shaped drift region include a lateral diffusion metal oxide semiconductor (LDMOS) FinFET having a substrate with a top surface and a fin attached to the top surface. The fin includes a source region having a first type of doping, an undoped gate-control region adjacent the source region, a drift region adjacent the undoped gate-control region opposite the source region, and a drain region. The amount of doping of the source region is greater than the amount of doping in the drift region. The drain region is adjacent to the drift region and has the same type of doping. The fin is tapered in the drift region, being wider closest to the undoped gate-control region and thinner closest to the drain region. A gate stack is attached to the top surface of the substrate and located with the undoped gate-control region.

摘要翻译： 具有成形漂移区域的高电压FinFET的装置和方法包括具有顶部表面的衬底和附接到顶表面的鳍的横向扩散金属氧化物半导体（LDMOS）FinFET。 散热片包括具有第一类掺杂的源极区域，与源极区域相邻的未掺杂栅极控制区域，与源极区域相对的未掺杂栅极控制区域相邻的漂移区域和漏极区域。 源极区域的掺杂量大于漂移区域中的掺杂量。 漏极区域与漂移区域相邻并且具有相同类型的掺杂。 翅片在漂移区域逐渐变细，最接近未掺杂的栅极控制区域更宽，最靠近漏极区域更薄。 栅极堆叠被附着到衬底的顶表面并且与未掺杂的栅极控制区域一起定位。

公开(公告)号：US20160380100A1

公开(公告)日：2016-12-29

申请号：US14751557

申请日：2015-06-26

申请人： GLOBALFOUNDRIES INC.

发明人： Andres Bryant ,  Edward J. Nowak ,  Robert R. Robison

IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L21/845 ,  G05F3/16 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/78696

摘要： An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

摘要翻译： 一种具有参考装置的集成电路及其形成方法。 公开了一种参考装置，其具有：实现为具有基本上未掺杂主体的长通道装置的完全耗尽的n型MOSFET; 以及用作具有基本上未掺杂的主体的长沟道器件实现的完全耗尽的p型MOSFET; 其中所述n型MOSFET和p型MOSFET串联连接并采用相同的栅极叠层，其中每个都具有电耦合到相应漏极的栅极以形成两个二极管，并且其中两个二极管处于导通状态和 根据施加在n型MOSFET和p型MOSFET上的电位的值的关闭状态。

公开(公告)号：US20160225680A1

公开(公告)日：2016-08-04

申请号：US14613570

申请日：2015-02-04

申请人： GLOBALFOUNDRIES INC.

发明人： Lyndon Ronald Logan ,  Edward J. Nowak ,  Robert R. Robison ,  Jonathan K. Winslow

IPC分类号： H01L21/66 ,  G01R31/26 ,  H01L29/45 ,  H01L21/67 ,  H01L21/8234 ,  H01L27/118

CPC分类号： H01L22/14 ,  G01R31/2621 ,  H01L21/823431 ,  H01L22/34 ,  H01L29/45

摘要： Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, a system includes a computer-implemented method of determining a laterally diffuse dopant profile in semiconductor structures by providing first and second semiconductor structures having plurality of gate array structures in a silicided region separated from each other by a first distance and second distance. A potential difference is applied across the plurality of gate array structures and resistances are determined. A linear-regression fit is performed on measured resistance versus the first distance and the second distance with an extrapolated x equals 0 and a y-intercept to determine a laterally diffused dopant-profile under the plurality of gate array structures based on a semiconductor device model.

摘要翻译： 各种实施例提供系统，计算机程序产品和计算机实现的方法。 在一些实施例中，系统包括计算机实现的方法，该方法通过提供具有多个栅极阵列结构的第一和第二半导体结构来确定半导体结构中的横向扩散掺杂物分布，所述第一和第二半导体结构在硅化区域中彼此分开第一距离和第二距离 。 在多个栅极阵列结构之间施加电势差，并确定电阻。 基于半导体器件模型，在测量的电阻相对于第一距离和第二距离上执行线性回归拟合，其中外推的x等于0和y截距以确定多个门阵列结构下的横向扩散的掺杂​​剂轮廓 。

公开(公告)号：US20150364491A1

公开(公告)日：2015-12-17

申请号：US14832166

申请日：2015-08-21

申请人： GLOBALFOUNDRIES Inc.

发明人： Viorel Ontalus ,  Robert R. Robison ,  Xin Wang

IPC分类号： H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L27/1203 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78621

摘要： A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.

摘要翻译： 半导体器件包括形成在绝缘体上半导体（SOI）衬底上的第一和第二栅极叠层。 SOI衬底包括介于主衬底层和有源半导体层之间的电介质层。 第一延伸植入部分邻近第一栅极堆叠设置，并且第二延伸注入部分邻近第二栅极堆叠设置。 晕轮植入物围绕沟槽连续延伸。 对接植入物在沟槽和电介质层之间延伸。 在暴露区域形成外延层，使得对接植入物介于外延层和电介质层之间。