公开(公告)号：US09349749B2

公开(公告)日：2016-05-24

申请号：US14832166

申请日：2015-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Viorel Ontalus ,  Robert R. Robison ,  Xin Wang

IPC: H01L21/331 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/1203 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78621

Abstract: A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.

Abstract translation: 半导体器件包括形成在绝缘体上半导体（SOI）衬底上的第一和第二栅极叠层。 SOI衬底包括介于主衬底层和有源半导体层之间的电介质层。 第一延伸植入部分邻近第一栅极堆叠设置，并且第二延伸注入部分邻近第二栅极堆叠设置。 晕轮植入物围绕沟槽连续延伸。 对接植入物在沟槽和电介质层之间延伸。 在暴露区域形成外延层，使得对接植入物介于外延层和电介质层之间。

公开(公告)号：US20150364491A1

公开(公告)日：2015-12-17

申请号：US14832166

申请日：2015-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Viorel Ontalus ,  Robert R. Robison ,  Xin Wang

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78621

Abstract: A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.

Abstract translation: 半导体器件包括形成在绝缘体上半导体（SOI）衬底上的第一和第二栅极叠层。 SOI衬底包括介于主衬底层和有源半导体层之间的电介质层。 第一延伸植入部分邻近第一栅极堆叠设置，并且第二延伸注入部分邻近第二栅极堆叠设置。 晕轮植入物围绕沟槽连续延伸。 对接植入物在沟槽和电介质层之间延伸。 在暴露区域形成外延层，使得对接植入物介于外延层和电介质层之间。

公开(公告)号：US09123783B2

公开(公告)日：2015-09-01

申请号：US13673549

申请日：2012-11-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xin Wang ,  Changyong Xiao ,  Yue Hu ,  Yong Meng Lee ,  Meng Luo ,  Jialin Weng ,  Wei Hua Tong ,  Wen-Pin Peng

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract translation: 本文提供集成电路和形成集成电路的方法。 在一个实施例中，形成集成电路的方法包括提供其中布置有嵌入式电触头的基底基板。 在基底基板上形成层间电介质，通过嵌入的电触头上的层间电介质蚀刻凹陷。 保护衬垫形成在凹部中并且在凹部中的嵌入式电触点的暴露表面上。 保护衬垫包括至少两个衬垫层，其在不同的蚀刻剂中具有实质上不同的蚀刻速率。 保护衬垫的一部分在嵌入的电触点的表面上被去除，以再次暴露凹陷中嵌入的电触点的表面。 在凹部中形成嵌入式电气互连。 嵌入式电互连覆盖在凹槽侧面上的保护衬垫。

公开(公告)号：US10453754B1

公开(公告)日：2019-10-22

申请号：US16021660

申请日：2018-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Haigou Huang ,  Qun Gao ,  Xin Wang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/324 ,  H01L21/02 ,  H01L21/225

Abstract: The present disclosure is directed to various methods of diffusing contact extension dopants in a transistor device and the resulting devices. One illustrative method includes forming a first contact opening between two adjacent gate structures formed above a first fin, the first contact opening exposing a first region of the first fin, forming a first contact recess in the first region, forming a first doped liner in the first contact recess, performing an anneal process to diffuse dopants from the first doped liner into the first fin to form a first doped contact extension region in the first fin, and performing a first epitaxial growth process to form a first source/drain region in the first contact recess.

公开(公告)号：US20140131881A1

公开(公告)日：2014-05-15

申请号：US13673549

申请日：2012-11-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xin Wang ,  Changyong Xiao ,  Yue Hu ,  Yong Meng Lee ,  Meng Luo ,  Jialin Weng ,  Wei Hua Tong ,  Wen-Pin Peng

IPC: H01L23/48 ,  H01L21/20 ,  H01L21/768

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76844

Abstract: Integrated circuits and methods of forming integrated circuits are provided herein. In an embodiment, a method of forming an integrated circuit includes providing a base substrate having an embedded electrical contact disposed therein. An interlayer dielectric is formed overlying the base substrate, and a recess is etched through the interlayer dielectric over the embedded electrical contact. A protecting liner is formed in the recess and over an exposed surface of the embedded electrical contact in the recess. The protecting liner includes at least two liner layers that have materially different etch rates in different etchants. A portion of the protecting liner is removed over the surface of the embedded electrical contact to again expose the surface of the embedded electrical contact in the recess. An embedded electrical interconnect is formed in the recess. The embedded electrical interconnect overlies the protecting liner on sides of the recess.

Abstract translation: 本文提供集成电路和形成集成电路的方法。 在一个实施例中，形成集成电路的方法包括提供其中布置有嵌入式电触头的基底基板。 在基底基板上形成层间电介质，通过嵌入的电触头上的层间电介质蚀刻凹陷。 保护衬垫形成在凹部中并且在凹部中的嵌入式电触点的暴露表面上。 保护衬垫包括至少两个衬垫层，其在不同的蚀刻剂中具有实质上不同的蚀刻速率。 保护衬垫的一部分在嵌入的电触点的表面上被去除，以再次暴露凹陷中嵌入的电触点的表面。 在凹部中形成嵌入式电气互连。 嵌入式电互连覆盖在凹槽侧面上的保护衬垫。

公开(公告)号：US09607989B2

公开(公告)日：2017-03-28

申请号：US14560049

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Yue Hu ,  Xin Wang ,  Yong Meng Lee ,  Wen-Pin Peng ,  Lun Zhao ,  Wei-Hua Tong

IPC: H01L27/092 ,  H01L29/165 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/06 ,  H01L21/768

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions.