公开(公告)号：US10692734B2

公开(公告)日：2020-06-23

申请号：US16171053

申请日：2018-10-25

Applicant: APPLIED MATERIALS, INC.

Inventor： Jong Mun Kim ,  Chentsau Chris Ying ,  He Ren ,  Srinivas D. Nemani ,  Ellie Yieh

IPC: H01L23/52 ,  H01L21/3213 ,  H01L23/532

Abstract: Methods and apparatus for processing a substrate and etching a nickel silicide layer are provided herein. In some embodiments, a method of etching a nickel silicide film in a semiconductor device include: contacting a nickel silicide film disposed on a substrate in a process chamber with an etching gas sufficient to form one or more soluble or volatile products in order to reduce or eliminate re-deposition of products formed from the nickel silicide film upon the nickel silicide film.

公开(公告)号：US09909213B2

公开(公告)日：2018-03-06

申请号：US14452228

申请日：2014-08-05

Applicant: Applied Materials, Inc.

Inventor： Sergio Fukuda Shoji ,  Hamid Noorbakhsh ,  Jong Mun Kim ,  Jason Della Rosa ,  Ajit Balakrishna

IPC: C23C16/44 ,  C23C16/455 ,  F15D1/02 ,  H01J37/32

CPC classification number: C23C16/45591 ,  C23C16/4412 ,  F15D1/025 ,  H01J37/32633 ,  H01J37/32834

Abstract: Embodiments of the present invention provide apparatus and methods for reducing non-uniformity and/or skews during substrate processing. One embodiment of the present invention provides a flow equalizer assembly for disposing between a vacuum port and a processing volume in a processing chamber. The flow equalizing assembly includes a first plate having at least one first opening, and a second plate having two or more second openings. The first and second plates define a flow redistributing volume therebetween, and the at least one first opening and the two or more second openings are staggered.

公开(公告)号：US09305804B2

公开(公告)日：2016-04-05

申请号：US14505138

申请日：2014-10-02

Applicant: Applied Materials, Inc.

Inventor： Jong Mun Kim ,  Jairaj J. Payyapilly

IPC: H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/311 ,  H01L21/3213 ,  H01J37/32

CPC classification number: H01L21/31116 ,  H01J37/32091 ,  H01J37/32165 ,  H01J2237/334 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32139

Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to the process of plasma etching an amorphous carbon layer. In one implementation, a method of etching a feature in an amorphous carbon layer is provided. The method comprises transferring a substrate including a patterned photoresist layer disposed above the amorphous carbon layer into an etching chamber, exposing the amorphous carbon layer to a fluorine-free etchant gas mixture including a fluorine-free halogen source gas and a passivation source gas and etching the amorphous carbon layer with a plasma of the fluorine-free etchant gas mixture. It has been found that plasma etching with a fluorine-free halogen based gas mixture reduces the formation of top critical dimension clogging oxides.

Abstract translation: 本文描述的实施方式通常涉及半导体制造，更具体地涉及等离子体蚀刻非晶碳层的工艺。 在一个实施方式中，提供了蚀刻无定形碳层中的特征的方法。 该方法包括将包括设置在无定形碳层上方的图案化光致抗蚀剂层的衬底转移到蚀刻室中，将无定形碳层暴露于包含无氟卤素源气体和钝化源气体的无氟蚀刻剂气体混合物和蚀刻 具有无氟蚀刻剂气体混合物的等离子体的无定形碳层。 已经发现用无氟卤素气体混合物的等离子体蚀刻减少了顶部临界尺寸堵塞氧化物的形成。

公开(公告)号：US12201030B2

公开(公告)日：2025-01-14

申请号：US18231414

申请日：2023-08-08

Applicant: Applied Materials, Inc.

Inventor： Minrui Yu ,  Wenhui Wang ,  Jaesoo Ahn ,  Jong Mun Kim ,  Sahil Patel ,  Lin Xue ,  Chando Park ,  Mahendra Pakala ,  Chentsau Chris Ying ,  Huixiong Dai ,  Christopher S. Ngai

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

公开(公告)号：US10685849B1

公开(公告)日：2020-06-16

申请号：US16400737

申请日：2019-05-01

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/321 ,  H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US20150097276A1

公开(公告)日：2015-04-09

申请号：US14491828

申请日：2014-09-19

Applicant: Applied Materials, Inc.

Inventor： Jong Mun Kim ,  Kenny L. Doan ,  Li Ling ,  Jairaj Payyapilly ,  Srinivas D. Nemani ,  Daisuke Shimizu ,  Yuju Huang

IPC: H01L29/792 ,  H01L21/66 ,  H01L21/3065

CPC classification number: H01L29/66833 ,  H01L21/31116

Abstract: An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C4F6H2 in a chamber of an etch reactor, ionizing the C4F6H2 containing gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions.

Abstract translation: 通过蚀刻工艺蚀刻具有交替的氧化物层和氮化物层的制品。 蚀刻工艺包括在蚀刻反应器的室中提供包含C 4 F 6 H 2的第一气体，使含有C 4 F 6 H 2的气体电离以产生包含多个离子的等离子体，并使用多个离子蚀刻该制品。

公开(公告)号：US20140342570A1

公开(公告)日：2014-11-20

申请号：US13912533

申请日：2013-06-07

Applicant: APPLIED MATERIALS, INC.

Inventor： Kenny Linh Doan ,  Daisuke Shimizu ,  Jong Mun Kim ,  Sergio Fukuda Shoji ,  Justin Phi ,  Katsumasa Kawasaki ,  Kartik Ramaswamy ,  James P. Cruse

IPC: H01L21/3065

CPC classification number: H01L21/3065

Abstract: The disclosure concerns a plasma-enhanced etch process in which chamber pressure and/or RF power level is ramped throughout the etch process.

Abstract translation: 本公开涉及等离子体增强蚀刻工艺，其中室压力和/或RF功率水平在整个蚀刻过程中倾斜。

公开(公告)号：US09589832B2

公开(公告)日：2017-03-07

申请号：US14071591

申请日：2013-11-04

Applicant: Applied Materials, Inc.

Inventor： Daisuke Shimizu ,  Jong Mun Kim

IPC: H01L21/302 ,  H01L21/768 ,  H01L21/311 ,  H01L21/283 ,  H01L21/67

CPC classification number: H01L21/76805 ,  H01L21/283 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/67069 ,  H01L21/76802 ,  H01L21/76879 ,  H01L21/76898

Abstract: One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas.

Abstract translation: 形成在衬底上沉积在第一绝缘层上的有机掩模层中的一个或多个开口。 使用第一含碘气体，通过有机掩模中的开口形成第一绝缘层中的一个或多个开口。 可以在有机掩模层上沉积抗反射层。 使用第二含碘气体，将抗反射层中的一个或多个开口形成为有机掩模层。 第一绝缘层可沉积在衬底上的第二绝缘层上。 可以使用第三含碘气体来形成第二绝缘层中的一个或多个开口。

公开(公告)号：US09299574B2

公开(公告)日：2016-03-29

申请号：US14157997

申请日：2014-01-17

Applicant: Applied Materials, Inc.

Inventor： Daisuke Shimizu ,  Jong Mun Kim

IPC: H01L21/3065 ,  B81C1/00 ,  H01L21/67 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01J37/32 ,  H01L27/115

CPC classification number: H01L21/3065 ,  B81C1/00531 ,  H01J37/32082 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/3244 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/67069 ,  H01L27/11556 ,  H01L27/11582

Abstract: Multilayered stacks having layers of silicon interleaved with layers of a dielectric, such as silicon dioxide, are plasma etched with non-corrosive process gas chemistries. Etching plasmas of fluorine source gases, such as SF6 and/or NF3 typically only suitable for dielectric layers, are energized by pulsed RF to achieve high aspect ratio etching of silicon/silicon dioxide bi-layers stacks without the addition of corrosive gases, such as HBr or Cl2. In embodiments, a mask open etch and the multi-layered stack etch are performed in a same plasma processing chamber enabling a single chamber, single recipe solution for patterning such multi-layered stacks. In embodiments, 3D NAND memory cells are fabricated with memory plug and/or word line separation etches employing a fluorine-based, pulsed-RF plasma etch.

Abstract translation: 具有与电介质层（诸如二氧化硅）交错的硅层的多层叠层用非腐蚀性工艺气体化学等离子体蚀刻。 氟源气体的蚀刻等离子体，例如通常仅适用于介电层的SF6和/或NF3，通过脉冲RF激励，以实现硅/二氧化硅双层堆叠的高纵横比蚀刻，而不加入腐蚀性气体，例如 HBr或Cl2。 在实施例中，掩模开口蚀刻和多层叠层蚀刻在相同的等离子体处理室中进行，从而能够实现用于图案化这种多层叠层的单室单配方解决方案。 在实施例中，使用采用氟基脉冲RF等离子体蚀刻的存储器插头和/或字线分离蚀刻来制造3D NAND存储器单元。

公开(公告)号：US11723283B2

公开(公告)日：2023-08-08

申请号：US16871779

申请日：2020-05-11

Applicant: Applied Materials, Inc.

Inventor： Minrui Yu ,  Wenhui Wang ,  Jaesoo Ahn ,  Jong Mun Kim ,  Sahil Patel ,  Lin Xue ,  Chando Park ,  Mahendra Pakala ,  Chentsau Chris Ying ,  Huixiong Dai ,  Christopher S. Ngai

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10N50/10 ,  G01R33/095 ,  G01R33/098 ,  G11C11/161 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.