公开(公告)号：US11056406B2

公开(公告)日：2021-07-06

申请号：US16688811

申请日：2019-11-19

Applicant: Applied Materials, Inc.

Inventor： Liyan Miao ,  Chentsau Ying ,  Xinhai Han ,  Long Lin

IPC: H01L51/00 ,  H01L21/66 ,  H01L21/02 ,  H01L21/3205 ,  C23C16/40 ,  C23C16/52 ,  C23C16/34 ,  C23C16/24 ,  C23C16/452 ,  H01J37/32 ,  C23C16/54 ,  H01L21/683 ,  C23C16/455 ,  C23C16/509 ,  H01L21/677 ,  H01L21/67

Abstract: Embodiments of the present technology may include a method of forming a stack of semiconductor layers. The method may include depositing a first silicon oxide layer on a substrate. The method may also include depositing a first silicon layer on the first silicon oxide layer. The method may include depositing a first silicon nitride layer on the first silicon layer. The method may further include depositing a second silicon layer on the first silicon nitride layer. In addition, the method may include depositing a stress layer on a side of the substrate opposite a side of the substrate with the first silicon oxide layer. The operations may form a structure of semiconductor layers, where the structure includes the first silicon oxide layer, the first silicon layer, the first silicon nitride layer, the second silicon layer, the substrate, and the stress layer. Other methods of reducing stress are described.

公开(公告)号：US09382625B2

公开(公告)日：2016-07-05

申请号：US14267865

申请日：2014-05-01

Applicant: Applied Materials, Inc.

Inventor： Jun Xue ,  Jingjing Liu ,  Yongmei Chen ,  Ludovic Godet ,  Chentsau Ying ,  Shambhu N. Roy

IPC: C23C16/56 ,  C23C16/27 ,  C23C16/46 ,  C23C16/455 ,  C23C16/505

CPC classification number: C23C16/56 ,  C23C16/27 ,  C23C16/272 ,  C23C16/452 ,  C23C16/45523 ,  C23C16/45557 ,  C23C16/46 ,  C23C16/505

Abstract: Methods for making a nanocrystalline diamond layer are disclosed herein. A method of forming a layer can include activating a deposition gas comprising an alkane and a hydrogen containing gas at a first pressure, delivering the activated deposition gas to the substrate at a second pressure which is less than the first pressure, forming a nanocrystalline diamond layer, treating the layer with an activated hydrogen containing gas to remove one or more polymers from the surface and repeating the cycle to achieve a desired thickness.

Abstract translation: 本文公开了制备纳米晶体金刚石层的方法。 形成层的方法可以包括在第一压力下激活包括烷烃和含氢气体的沉积气体，在小于第一压力的第二压力下将活化的沉积气体输送到衬底，形成纳米晶体金刚石层 用活化的含氢气体处理层以从表面去除一种或多种聚合物并重复该循环以达到所需的厚度。

公开(公告)号：US12057329B2

公开(公告)日：2024-08-06

申请号：US15828112

申请日：2017-11-30

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Chentsau Ying ,  Srinivas Nemani ,  Viachslav Babayan ,  Michael Stowell

IPC: H01L21/00 ,  H01J37/32 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687 ,  H01L21/3105

CPC classification number: H01L21/67069 ,  H01J37/32146 ,  H01J37/32706 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/68735 ,  H01J2237/334 ,  H01L21/3105

Abstract: Semiconductor systems and methods may include methods of performing selective etches that include modifying a material on a semiconductor substrate. The substrate may have at least two exposed materials on a surface of the semiconductor substrate. The methods may include forming a low-power plasma within a processing chamber housing the semiconductor substrate. The low-power plasma may be a radio-frequency (“RF”) plasma, which may be at least partially formed by an RF bias power operating between about 10 W and about 100 W in embodiments. The RF bias power may also be pulsed at a frequency below about 5,000 Hz. The methods may also include etching one of the at least two exposed materials on the surface of the semiconductor substrate at a higher etch rate than a second of the at least two exposed materials on the surface of the semiconductor substrate.

公开(公告)号：US10858727B2

公开(公告)日：2020-12-08

申请号：US15600247

申请日：2017-05-19

Applicant: Applied Materials, Inc.

Inventor： Jingjing Liu ,  Zhong Qiang Hua ,  Adolph Miller Allen ,  Michael W. Stowell ,  Srinivas D. Nemani ,  Chentsau Ying ,  Bhargav Citla ,  Viachslav Babayan ,  Andrej Halabica

IPC: H01J37/34 ,  C23C14/06 ,  C23C14/35 ,  H01J37/32 ,  C23C14/54 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  C23C14/34

Abstract: A deposited amorphous carbon film includes at least 95% carbon. A percentage of sp3 carbon-carbon bonds present in the amorphous carbon film exceeds 30%, and a hydrogen content of the amorphous carbon film is less than 5%. A process of depositing amorphous carbon on a workpiece includes positioning the workpiece within a process chamber and positioning a magnetron assembly adjacent to the process chamber. The magnetron assembly projects a magnetic field into the process chamber. The method further includes providing a carbon target such that the magnetic field extends through the carbon target toward the workpiece. The method further includes providing a source gas to the process chamber, and providing pulses of DC power to a plasma formed from the source gas within the process chamber. The pulses of DC power are supplied in pulses of 40 microseconds or less, that repeat at a frequency of at least 4 kHz.

公开(公告)号：US10685849B1

公开(公告)日：2020-06-16

申请号：US16400737

申请日：2019-05-01

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/321 ,  H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US09502262B2

公开(公告)日：2016-11-22

申请号：US14833858

申请日：2015-08-24

Applicant: Applied Materials, Inc.

Inventor： Yongmei Chen ,  Christopher S. Ngai ,  Jingjing Liu ,  Jun Xue ,  Chentsau Ying ,  Ludovic Godet

IPC: C23C16/27 ,  H01L21/31 ,  H01L21/311 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L27/115

CPC classification number: H01L21/0332 ,  C23C16/26 ,  C23C16/27 ,  C23C16/274 ,  C23C16/279 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/49 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518

Abstract: A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.

Abstract translation: 本文公开了用于形成半导体器件的纳米晶体金刚石层及其使用方法。 该器件可以包括具有处理表面和支撑表面的衬底，形成在处理表面上的器件层和形成在处理层上的纳米晶体金刚石层，该纳米晶体金刚石层的平均晶粒尺寸在2nm和5nm之间 。 该方法可以包括将衬底定位在处理室中，在处理表面上沉积器件层，在器件层上沉积纳米晶体金刚石层，平均晶粒尺寸在2nm和5nm之间的纳米晶体金刚石层，图案化和 蚀刻纳米晶体金刚石层，蚀刻器件层以形成特征并从器件层的表面灰化纳米晶体金刚石层。

公开(公告)号：US20160240385A1

公开(公告)日：2016-08-18

申请号：US15000273

申请日：2016-01-19

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Chentsau Ying ,  Srinivas D. Nemani

IPC: H01L21/3065 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L21/02071 ,  H01L21/28035 ,  H01L21/32137

Abstract: The present disclosure provides methods for removing gate electrode residuals from a gate structure after a gate electrode patterning process. In one example, a method for forming high aspect ratio features in a gate electrode layer in a gate structure includes performing an surface treatment process on gate electrode residuals remaining on a gate structure disposed on a substrate, selectively forming a treated residual in the gate structure on the substrate with some untreated regions nearby in the gate structure, and performing a remote plasma residual removal process to remove the treated residual from the substrate.

Abstract translation: 本公开提供了在栅电极图案化工艺之后从栅极结构去除栅电极残留的方法。 在一个示例中，用于在栅极结构中的栅极电极层中形成高纵横比特征的方法包括对残留在设置在基板上的栅极结构上的栅电极残余物进行表面处理处理，在栅极结构中选择性地形成经处理的残留物 在衬底上具有栅极结构附近的一些未处理区域，以及执行远程等离子体残留去除工艺以从衬底去除经处理的残余物。

公开(公告)号：US20200350178A1

公开(公告)日：2020-11-05

申请号：US16901210

申请日：2020-06-15

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC: H01L21/3213

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US10570506B2

公开(公告)日：2020-02-25

申请号：US15820777

申请日：2017-11-22

Applicant: Applied Materials, Inc.

Inventor： Bhargav Citla ,  Jingjing Liu ,  Zhong Qiang Hua ,  Chentsau Ying ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: C23C14/00 ,  C23C14/06 ,  C23C14/34 ,  C23C14/35 ,  H01J37/34 ,  H01L21/02 ,  H01L21/033

Abstract: Embodiments of the present disclosure generally describe methods for depositing an amorphous carbon layer onto a substrate, including over previously formed layers on the substrate, using a high power impulse magnetron sputtering (HiPIMS) process, and in particular, biasing of the substrate during the deposition process and flowing a nitrogen source gas and/or a hydrogen source gas into the processing chamber in addition to an inert gas to improve the morphology and film stress of the deposited amorphous carbon layer.

公开(公告)号：US09865464B2

公开(公告)日：2018-01-09

申请号：US15348170

申请日：2016-11-10

Applicant: Applied Materials, Inc.

Inventor： Yongmei Chen ,  Christopher S. Ngai ,  Jingjing Liu ,  Jun Xue ,  Chentsau Ying ,  Ludovic Godet

IPC: H01L21/033 ,  H01L29/49 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/02 ,  H01L21/311 ,  C23C16/27 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L21/0332 ,  C23C16/26 ,  C23C16/27 ,  C23C16/274 ,  C23C16/279 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/49 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518

Abstract: A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.