公开(公告)号：US09695503B2

公开(公告)日：2017-07-04

申请号：US14820152

申请日：2015-08-06

Applicant: Applied Materials, Inc.

Inventor： Michael W. Stowell ,  Yongmei Chen

IPC: C23C14/34 ,  C23C14/35 ,  H01L21/02 ,  C23C14/06 ,  C23C16/27 ,  C23C16/50

CPC classification number: C23C14/35 ,  C23C14/0611 ,  C23C16/272 ,  C23C16/50 ,  H01L21/02115 ,  H01L21/02266

Abstract: Methods for depositing a nanocrystalline diamond layer are disclosed herein. The method can include delivering a sputter gas to a substrate positioned in a processing region of a first process chamber, the first process chamber having a carbon-containing sputter target, delivering an energy pulse to the sputter gas to create a sputtering plasma, the sputtering plasma having a sputtering duration, the energy pulse having an average power between 1 W/cm2 and 10 W/cm2 and a pulse width which is less than 100 μs and greater than 30 μs, the sputtering plasma being controlled by a magnetic field, the magnetic field being less than 300. Gauss, and delivering the sputtering plasma to the sputter target to form an ionized species, the ionized species forming a crystalline carbon-containing layer on the substrate.

公开(公告)号：US09412613B2

公开(公告)日：2016-08-09

申请号：US14574928

申请日：2014-12-18

Applicant: Applied Materials, Inc.

Inventor： Pramit Manna ,  Abhijit Basu Mallick ,  Ludovic Godet ,  Yongmei Chen ,  Jun Xue ,  Mukund Srinivasan ,  Ellie Y. Yieh ,  Srinivas D. Nemani

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L21/3086 ,  H01L21/31144 ,  H01L21/31155

Abstract: Embodiments described herein provide for a method of forming an etch selective hardmask. An amorphous carbon hardmask is implanted with various dopants to increase the hardness and density of the hardmask. The ion implantation of the amorphous carbon hardmask also maintains or reduces the internal stress of the hardmask. The etch selective hardmask generally provides for improved patterning in advanced NAND and DRAM devices.

Abstract translation: 本文描述的实施例提供了形成蚀刻选择性硬掩模的方法。 非晶碳硬掩模被植入各种掺杂剂以增加硬掩模的硬度和密度。 无定形碳硬掩模的离子注入还保持或减少硬掩模的内部应力。 蚀刻选择性硬掩模通常提供高级NAND和DRAM器件中的改进的图案化。

公开(公告)号：US20170372960A1

公开(公告)日：2017-12-28

申请号：US15700631

申请日：2017-09-11

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Huixiong Dai ,  Yongmei Chen ,  He Ren ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532

Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

公开(公告)号：US09382625B2

公开(公告)日：2016-07-05

申请号：US14267865

申请日：2014-05-01

Applicant: Applied Materials, Inc.

Inventor： Jun Xue ,  Jingjing Liu ,  Yongmei Chen ,  Ludovic Godet ,  Chentsau Ying ,  Shambhu N. Roy

IPC: C23C16/56 ,  C23C16/27 ,  C23C16/46 ,  C23C16/455 ,  C23C16/505

CPC classification number: C23C16/56 ,  C23C16/27 ,  C23C16/272 ,  C23C16/452 ,  C23C16/45523 ,  C23C16/45557 ,  C23C16/46 ,  C23C16/505

Abstract: Methods for making a nanocrystalline diamond layer are disclosed herein. A method of forming a layer can include activating a deposition gas comprising an alkane and a hydrogen containing gas at a first pressure, delivering the activated deposition gas to the substrate at a second pressure which is less than the first pressure, forming a nanocrystalline diamond layer, treating the layer with an activated hydrogen containing gas to remove one or more polymers from the surface and repeating the cycle to achieve a desired thickness.

Abstract translation: 本文公开了制备纳米晶体金刚石层的方法。 形成层的方法可以包括在第一压力下激活包括烷烃和含氢气体的沉积气体，在小于第一压力的第二压力下将活化的沉积气体输送到衬底，形成纳米晶体金刚石层 用活化的含氢气体处理层以从表面去除一种或多种聚合物并重复该循环以达到所需的厚度。

公开(公告)号：US09502262B2

公开(公告)日：2016-11-22

申请号：US14833858

申请日：2015-08-24

Applicant: Applied Materials, Inc.

Inventor： Yongmei Chen ,  Christopher S. Ngai ,  Jingjing Liu ,  Jun Xue ,  Chentsau Ying ,  Ludovic Godet

IPC: C23C16/27 ,  H01L21/31 ,  H01L21/311 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L27/115

CPC classification number: H01L21/0332 ,  C23C16/26 ,  C23C16/27 ,  C23C16/274 ,  C23C16/279 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/49 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518

Abstract: A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.

Abstract translation: 本文公开了用于形成半导体器件的纳米晶体金刚石层及其使用方法。 该器件可以包括具有处理表面和支撑表面的衬底，形成在处理表面上的器件层和形成在处理层上的纳米晶体金刚石层，该纳米晶体金刚石层的平均晶粒尺寸在2nm和5nm之间 。 该方法可以包括将衬底定位在处理室中，在处理表面上沉积器件层，在器件层上沉积纳米晶体金刚石层，平均晶粒尺寸在2nm和5nm之间的纳米晶体金刚石层，图案化和 蚀刻纳米晶体金刚石层，蚀刻器件层以形成特征并从器件层的表面灰化纳米晶体金刚石层。

公开(公告)号：US12249489B2

公开(公告)日：2025-03-11

申请号：US18131997

申请日：2023-04-07

Applicant: Applied Materials, Inc.

Inventor： Yue Chen ,  Jinyu Lu ,  Yongmei Chen ,  Jinxin Fu ,  Zihao Yang ,  Mingwei Zhu ,  Takashi Kuratomi ,  Rami Hourani ,  Ludovic Godet ,  Qun Jing ,  Jingyi Yang ,  David Masayuki Ishikawa

IPC: H01J37/32 ,  H01J7/02

Abstract: A method of processing an optical device is provided, including: positioning an optical device on a substrate support in an interior volume of a process chamber, the optical device including an optical device substrate and a plurality of optical device structures formed over the optical device substrate, each optical device structure including a bulk region formed of silicon carbide and one or more surface regions formed of silicon oxycarbide. The method further includes providing one or more process gases to the interior volume of the process chamber, and generating a plasma of the one or more process gases in the interior volume for a first time period when the optical device is on the substrate support, and stopping the plasma after the first time period. A carbon content of the one or more surface regions of each optical device structure is reduced by at least 50% by the plasma.

公开(公告)号：US10957590B2

公开(公告)日：2021-03-23

申请号：US16669082

申请日：2019-10-30

Applicant: Applied Materials, Inc.

Inventor： Wenhui Wang ,  Huixiong Dai ,  Christopher S. Ngai ,  Liqi Wu ,  Wenyu Zhang ,  Yongmei Chen ,  Hao Chen ,  Keith Tatseun Wong ,  Ke Chang

IPC: H01L21/768 ,  H01L23/535 ,  H01L21/02 ,  H01L21/033 ,  H01L21/311

Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved.

公开(公告)号：US10927449B2

公开(公告)日：2021-02-23

申请号：US15857384

申请日：2017-12-28

Applicant: Applied Materials, Inc.

Inventor： Jingjing Liu ,  Ludovic Godet ,  Srinivas D. Nemani ,  Yongmei Chen ,  Anantha K. Subramani

IPC: C23C14/34 ,  H01L21/265 ,  H01J37/34 ,  C23C14/50 ,  C23C14/35 ,  C23C14/48 ,  H01J37/32 ,  H01L21/223

Abstract: Embodiments of the present disclosure provide a sputtering chamber with in-situ ion implantation capability. In one embodiment, the sputtering chamber comprises a target, an RF and a DC power supplies coupled to the target, a support body comprising a flat substrate receiving surface, a bias power source coupled to the support body, a pulse controller coupled to the bias power source, wherein the pulse controller applies a pulse control signal to the bias power source such that the bias power is delivered either in a regular pulsed mode having a pulse duration of about 100-200 microseconds and a pulse repetition frequency of about 1-200 Hz, or a high frequency pulsed mode having a pulse duration of about 100-300 microseconds and a pulse repetition frequency of about 200 Hz to about 20 KHz, and an exhaust assembly having a concentric pumping port formed through a bottom of the processing chamber.

公开(公告)号：US09865464B2

公开(公告)日：2018-01-09

申请号：US15348170

申请日：2016-11-10

Applicant: Applied Materials, Inc.

Inventor： Yongmei Chen ,  Christopher S. Ngai ,  Jingjing Liu ,  Jun Xue ,  Chentsau Ying ,  Ludovic Godet

IPC: H01L21/033 ,  H01L29/49 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/02 ,  H01L21/311 ,  C23C16/27 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L21/0332 ,  C23C16/26 ,  C23C16/27 ,  C23C16/274 ,  C23C16/279 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/49 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518

Abstract: A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.

公开(公告)号：US09761489B2

公开(公告)日：2017-09-12

申请号：US13987667

申请日：2013-08-20

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Huixiong Dai ,  Yongmei Chen ,  He Ren ,  Mehul Naik

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/53257 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.